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Spill registers not available


As I stated on other emails I'm writing a backend. I'm facing a
problem regarding register modes.
The thing is: I don't know how to handle non-SI modes. I've read many
backends for different arches but I don't really get it, sorry.

In my case I've started with a x86 backend. This arch has 4
byte-accessible regs, therefore I implemented the macro
HARD_REGNO_MODE_OK to return false for those non QImode accessible
regs (in QImode of course).

This seems to work great with the inconvenient that sometimes I hit this error:

libstdc++-v3/include/bits/streambuf.tcc:110:5: error: could not find a
spill register
(insn 72 146 73 7 (parallel [
            (set (mem:SI (plus:SI (reg/f:SI 7 %esp)
                        (const_int 4 [0x4])) [0 S4 A32])
                (ashift:SI (subreg:SI (mem:QI (reg/v/f:SI 3 %ebx
[orig:42 __s ] [42]) [0 MEM[(const char_type &)__s_98]+0 S1 A8]) 0)
                    (const_int 24 [0x18])))
            (clobber (reg:CC 10 eflags))
        ]) /home/david/uclibc/uclibc-buildroot-custom/output/build/host-gcc-final-gcc-4_7_3-release/build/i686-buildroot-linux-gnu/libstdc++-v3/include/bits/char_traits.h:287
7 {ashlsi3}
     (expr_list:REG_UNUSED (reg:CC 10 eflags)

Debugging it a little it seems that it tries to spill the memory
operand into a register, but it fails. I don't know why it picks a
non-byte accessible reg and therefore it fails (I guess because the
other ones are in use).

Another question would be: My ashift operator takes SI operands and
the memory operand is byte. Could I define an expand to set an SI reg
from a QI mem element by doing zero expansion (or sign extension)? And

Thanks a lot!

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