Re: Reorg a reorg.c comment

[John David Anglin <dave dot anglin at bell dot net>]

On 24-Nov-12, at 9:19 PM, Steven Bosscher wrote:

> +;; This machine description is inspired by sparc.md and (to a lesser
> +;; extend) mips.md.

Change "extend" to "extent".  Don't need parentheses.

> +
> +;; Possible improvements, if anyone is still interested in working on
> +;; improving this machine description in 2012:

Please remove the "if anyone ..." part.

> +;;
> +;; * With PA2.0, most computational instructions can conditionally  
> nullify
> +;;   the execution of the following instruction.  Nullification is  
> performed

Add statement to effect that nullification is a very efficient for
it does not cause the instruction pipeline to stall.

> +;;   conditionally based on the outcome of a test specified in the  
> opcode.
> +;;   The test result is stored in PSW[N] and can only be used to  
> nullify the
> +;;   instruction following immediately after the test.  For example:
> +;;
> +;;	ldi 10,%r26			ldi 10,%r26
> +;;	ldi 5,%r25			ldi 5,%r25
> +;;	sub,< %r26,%r25,%r28		sub,> %r26,%r25,%r28
> +;;	sub   %r28,%r25,%r28		sub   %r28,%r25,%r28
> +;;	; %r28 == 0			; %r28 == 5

Find the parallel layout somewhat confusing.  Maybe we just need one.

> +;;
> +;;   This could be tricky to implement because the result of the  
> test has
> +;;   to be propagated one instruction forward, which, in the worst  
> case,
> +;;   would involve (1) adding a fake register for PSW[N]; (2)  
> adding the
> +;;   variants of the computational instructions that set or consume  
> this
> +;;   fake register.  The cond_exec infrastructure is probably not  
> helpful
> +;;   for this.
> +;;

Another improvement might be to implement the static branch prediction
hints for conditional branches (Section I-3 in PA-RISC 2.0  
Architecture).

> ;;- See file "rtl.def" for documentation on define_insn, match_*,  
> et. al.


Dave
--
John David Anglin	dave.anglin@bell.net