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Hello Vlad,Ops. I'll look at this. As I remember, I thought about the problem. But I did not wanted to update live info because it is expensive and constraint equiv substitution by safe cases. Somehow I added unsafe cases (containing pseudos) and even added the code to spill pseudos in substitutions when they start to conflict with others because of widening live ranges but forgot about live info. I'll try to fix it as soon as possible.
Is it intentional that DF_LR_IN and DF_LR_OUT are not updated after "Updating elimination of equiv for reg..."? I have some checking in place in process_bb_lives at the end of the function, and it triggers on the test case. (Checking code and test case is at the end of this e-mail.) It show:
LIVEIN-mismatch in bb 5: 66, 69, 66, 69, 73 73 t.c: In function 'get_mem_attrs': t.c:47:1: internal compiler error: in process_bb_lives, at lra-lives.c:866 } ^
And that's correct if you look at the LR_IN set of basic block 5 in the IRA (.193r.ira) dump:
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