This is the mail archive of the
mailing list for the GCC project.
RE: Expanding instructions with condition codes inter-deps
>There are lots of parts of the compiler that don't optimize well when an insn has more than one output. For the normal insn, just clobber the flags; don't include a second SET.
Yes, but... isn't the whole point of CC modeling that you can take advantage of the CC left around by an instruction? Typically in machines with condition codes, you can eliminate test instructions (compare with zero) if the previous instruction has that variable as its output. But if we're discouraged from writing insns with CC outputs as normal practice, and if the compiler doesn't handle such constructs well in optimization, what then?
Is cc0 any better here? In cc0 style condition code handling, the condition codes output is implicit rather than explicitly stated. Does that help, or hurt, or make no difference for the point you mentioned?