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Re: should sync builtins be full optimization barriers?
On Sep 11, 2011, at 15:11, Jakub Jelinek wrote:
> On Sun, Sep 11, 2011 at 03:00:11PM -0400, Geert Bosch wrote:
>> Also, for relaxed order atomic operations we would only need a single
>> fence between two accesses (by a thread) to the same atomic object.
>
> I'm not aware of any CPUs that would need any kind of fences for that.
> Nor the compiler should need any fences for that, MEMs that may (or even are
> known to be aliased) aren't reordered.
I guess for CPUs with TSO that might be right wrt. the hardware.
I wouldn't say it is true in general.
But all atomic operations on an atomic object M should have
a total order. That means the compiler
So for some atomic int X, with relaxed ordering:
if (X == 0) X = 1;
else X = 2;
we can't optimize that to:
X = 1;
if (X != 0) X = 2;
Do you agree?
-Geert