Re: Describing multi-register values in RTL

[Ian Lance Taylor <iant at google dot com>]

FrÃdÃric RISS <frederic.riss@gmail.com> writes:

>> The lower subreg pass will do that for you if you have the right set of
>> insns.
>
> Could you expand a bit on what the 'right set of instructions' is or
> even better give an example of an md file where we could find an
> example?

E.g., on a 32-bit system, start with a normal adddi3 insn which just
does
   (set (reg:DI) (plus:DI (op) (op)))
That will work for combine, the RTL CSE and loop optimizers, etc.

Then have a splitter for that insn into something like
   (parallel
    (set (reg:SI) (plus:SI (op-low) (op-low)))
    (set (reg:SI) (plus:SI (plus:SI (op-high) (op-high))
                           (truncate:SI
                            (lshiftrt:DI
                             (plus:DI
                              (zero_extend:DI (op-low))
                              (zero_extend:DI (op-high))))))))

That split will happen after the RTL passes which care about the DImode
add.  The point of the parallel is to express a DImode addition as a
pair of SImode additions, adding in the carry bit to the upper value.

The lower-subreg pass will run after the split.  It will see that the
value is accessed only as SImode registers and will split it into two
independent SImode registers.  That will let the register allocator
handle them separately.

Then you need another splitter which takes the parallel above and splits
it into two independent insns, which can be scheduled independently.

Ian