constraints and predicates

[roy rosen <roy dot 1rosen at gmail dot com>]

Hi All,

If I don't use a constraint, is it possible that during ira I get a
register which is not acceptable by the predicate?
In my port I have the following to support HW loops:

(define_predicate "lc_operand"
    (match_operand 0 "register_operand")
{
        unsigned int regno;
        if (GET_CODE (op) == SUBREG)
            op = SUBREG_REG (op);
        regno = REGNO (op);
        return (regno >= FIRST_PSEUDO_REGISTER ||
REGNO_REG_CLASS(regno) == LC_REGS);
}
)

(define_expand "doloop_end"
  [(use (match_operand 0 "" ""))	; loop pseudo
   (use (match_operand 1 "" ""))	; iterations; zero if unknown
   (use (match_operand 2 "" ""))	; max iterations
   (use (match_operand 3 "" ""))	; loop level
   (use (match_operand 4 "" ""))]       ; label
  ""
  {
    if (INTVAL (operands[3]) > 4
    )
        FAIL;
    emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0]));
    DONE;
  }
)

(define_insn "doloop_end_internal"
  [(set (pc)
	(if_then_else (ne (match_operand:SI 1 "lc_operand" "")
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))
   (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))]
  ""
  "doloop_end%b1 %!"
)

I see that during ira operand 1 in doloop_end_internal is getting
"best GENERAL_REGS" and eventually ends up as a register of a class
other than LC_REGS.
I thought that if I have predicate lc_operand then I don't need a
constraint since all other register classes would be rejected in all
stages for this operand.
What might be the problem here?

Thanks, Roy.