This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Reload going wrong for addition.

Hello all,

I doing a port for a 32bit target for GCC 4.4.0. I am getting the
following error:

rd_er.c:19: error: insn does not satisfy its constraints:
(insn 5 35 34 2 rd_er.c:8 (set (reg:SI 16 r0)
        (plus:SI (reg:SI 16 r0)
            (reg:SI 2 d2))) 57 {addsi3} (expr_list:REG_EQUAL (plus:SI
(reg/f:SI 49 sp)
            (const_int -65544 [0xfffffffffffefff8]))

My target has 16 data registers and 16 address registers. All are
32bit registers.
The target also has a dedicated stack pointer.
There is no move operation possible between SP and data regs.
There is no provision for addition between data and address registers.
R7 is used as Frame Pointer.

Pattern for addition

(define_insn "add<mode>3"
  [(set (match_operand:INT 0 "register_operand"
                                             "=d, t, k, a, a, t, k, t, d")
        (plus:INT(match_operand:INT 1 "register_operand"
                                               "0, 0, 0, t, k, 0, 0, 0, 0")
                 (match_operand:INT 2 "nonmemory_operand"
                                               "J, J, J, L, L, t, t, k, d")))]

The constraints used are -
;;    d  -   Data registers [D0 - D15]
;;    a  -   Address registers [R0 - R15]
;;    t   -   Address and Index registers
;;    k   -  Stack Pointer
;;    J   -   Unsigned 5bit immediate
;;    L   -   Signed 16bit immediate

Since there is no move operation between SP and data regs i have
specified 12 as the register_move_cost between them. I also return the
reload class as address register class in preferred_reload_class when
the rtx is SP.

b4 ira pass

(insn 5 2 12 2 rd_er.c:8 (set (reg/v/f:SI 60 [ bufptr ])
        (reg/f:SI 23 r7)) 43 {*movsi_internal} (nil))

Input for reload pass

(insn 5 2 12 2 rd_er.c:8 (set (reg/v/f:SI 7 d7 [orig:60 bufptr ] [60])
        (plus:SI (reg/f:SI 49 sp)
            (const_int -65536 [0xffffffffffff0000]))) 57 {addsi3}
(expr_list:REG_EQUAL (plus:SI (reg/f:SI 49 sp)
            (const_int -65536 [0xffffffffffff0000]))

After IRA

Reloads for insn # 5
Reload 0: reload_in (SI) = (reg/f:SI 49 sp)
        reload_out (SI) = (reg/v/f:SI 7 d7 [orig:60 bufptr ] [60])
        HIGH_OR_LOW, RELOAD_OTHER (opnum = 0)
        reload_in_reg: (reg/f:SI 49 sp)
        reload_out_reg: (reg/v/f:SI 7 d7 [orig:60 bufptr ] [60])
        reload_reg_rtx: (reg:SI 16 r0)
Reload 1: reload_in (SI) = (const_int -65544 [0xfffffffffffefff8])
        DALU_REGS, RELOAD_FOR_INPUT (opnum = 2)
        reload_in_reg: (const_int -65544 [0xfffffffffffefff8])
        reload_reg_rtx: (reg:SI 2 d2)

(insn 5 35 34 2 rd_er.c:8 (set (reg:SI 16 r0)
        (plus:SI (reg:SI 16 r0)
            (reg:SI 2 d2))) 57 {addsi3} (expr_list:REG_EQUAL (plus:SI
(reg/f:SI 49 sp)
            (const_int -65544 [0xfffffffffffefff8]))

The reload pass chooses the final alternative as the goal for reloading.
Since the input instruction already has data register as the
destination the constraint combination (t, 0, t) looses to (d, 0, d),
since the last combination requires least amount copying for
constraint matching (or so the reload pass believes). There are cases
when reload fixes the add pattern and those are when either the
destination is address register or there is no stack pointer involved.
But otherwise i am getting this ICE. I am not sure how to over come

Hope someone suggests me a solution.


P.S Can i have commutative operation for the constraint combination
(t, 0, t) i.e (t, %0, t). If so what will be the output template?

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]