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Re: Extending constraints using register subclasses


On Mon, May 11, 2009 at 04:45:26PM -0700, Jamie Prescott wrote:
> 
> Hi!
> I wanted to add finer (one per) register subclasses, so that I can more finely control
> the register placement inside the inline assembly.
> These are the relevant definitions inside my include file:
> 
> enum reg_class
> {
>         NO_REGS = 0,
>         GENERAL_REGS,
>         X_REGS,
>         R0_REG, R1_REG, R2_REG, R3_REG,
>         R4_REG, R5_REG, R6_REG, R7_REG,
>         X0_REG, X1_REG, X2_REG, X3_REG,
>         X4_REG, X5_REG, X6_REG, X7_REG,
>         ALL_REGS,
>         LIM_REG_CLASSES
> };
> 
> #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
> 
> /* Give names of register classes as strings for dump file.  */
> 
> #define REG_CLASS_NAMES                                         \
>         {                                                       \
>                 "NO_REGS",                                      \
>                         "GENERAL_REGS",                         \
>                         "X_REGS",                               \
>                         "R0_REG", "R1_REG", "R2_REG", "R3_REG", \
>                         "R4_REG", "R5_REG", "R6_REG", "R7_REG", \
>                         "X0_REG", "X1_REG", "X2_REG", "X3_REG", \
>                         "X4_REG", "X5_REG", "X6_REG", "X7_REG", \
>                         "ALL_REGS",                             \
>                         "LIM_REGS"                              \
>                         }
> 
> /* Define which registers fit in which classes.
>    This is an initializer for a vector of HARD_REG_SET
>    of length N_REG_CLASSES.  */
> 
> #define REG_CLASS_CONTENTS                                              \
>         {                                                               \
>                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS      */ \
>                 { 0xffffffff, 0x007fffff, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
>                 { 0x00000000, 0xff800000, 0xffffffff, 0x007fffff }, /* X_REGS   */ \
>                 { 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* R0_REG      */ \
>                 { 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* R1_REG      */ \
>                 { 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* R2_REG      */ \
>                 { 0x00000008, 0x00000000, 0x00000000, 0x00000000 }, /* R3_REG      */ \
>                 { 0x00000010, 0x00000000, 0x00000000, 0x00000000 }, /* R4_REG      */ \
>                 { 0x00000020, 0x00000000, 0x00000000, 0x00000000 }, /* R5_REG      */ \
>                 { 0x00000040, 0x00000000, 0x00000000, 0x00000000 }, /* R6_REG      */ \
>                 { 0x00000080, 0x00000000, 0x00000000, 0x00000000 }, /* R7_REG      */ \
>                 { 0x00000000, 0x00800000, 0x00000000, 0x00000000 }, /* X0_REG   */ \
>                 { 0x00000000, 0x01000000, 0x00000000, 0x00000000 }, /* X1_REG   */ \
>                 { 0x00000000, 0x02000000, 0x00000000, 0x00000000 }, /* X2_REG   */ \
>                 { 0x00000000, 0x04000000, 0x00000000, 0x00000000 }, /* X3_REG   */ \
>                 { 0x00000000, 0x08000000, 0x00000000, 0x00000000 }, /* X4_REG   */ \
>                 { 0x00000000, 0x10000000, 0x00000000, 0x00000000 }, /* X5_REG   */ \
>                 { 0x00000000, 0x20000000, 0x00000000, 0x00000000 }, /* X6_REG   */ \
>                 { 0x00000000, 0x40000000, 0x00000000, 0x00000000 }, /* X7_REG   */ \
>                 { 0xffffffff, 0xffffffff, 0xffffffff, 0x007fffff }, /* ALL_REGS         */ \
>                         }

In addition to the ordering GENERAL_REGS after the R/X_REGS, you didn't mention
defining IRA_COVER_CLASSES.  With the new IRA register allocator, you need to
define a cover class for all registers that can be moved back and forth.  For
your setup, I would imagine the following would work:

#define IRA_COVER_CLASS { GENERAL_REGS }

If you don't define an IRA_COVERT_CLASS, then the compiler assumes each
register class is unique, and it can't copy between them.

I ran into this on the power7 support.  On previous power machines, you have
two classes of registers FLOAT_REGS and ALTIVEC_REGS (in addition to the GPRs
and other registers), but the new VSX instruction set has a merged register set
that both the traditional floating point registers and the altivec vector
registers are a set of.  I found I needed to have a different cover class for
VSX using the VSX_REGS class which is the union of the two, and FLOAT_REGS,
ALTIVEC_REGS for the pre-vsx code, and switch which is used in the
ira_cover_classes target hook.

-- 
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meissner@linux.vnet.ibm.com


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