This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: Setting ARM PIC register (Was: RE: GCC 4.5.0 Status Report (2009-05-05))


Michael Matz wrote:
> Hi,
> 
> On Wed, 6 May 2009, Joern Rennecke wrote:
> 
>> Richard Earnshaw:
>>> That won't work because the PIC register on ARM is a pseudo, so
>>> generating it during prologue generation is too late.  It needs to exist
>>> before data flow analysis starts on the RTL.
>> How about emitting a set at each place the PIC register is needed,
>> and making sure that gcse will will common these sets where
>> appropriate?
> 
> Seems overly twisted to me.  Richard: no I was confused, you indeed can't 
> wait until prologue emission, sorry.  Hmm, so we need some place to either 
> remember the instruction sequence until expansion is done (or at least 
> expansion of the basic blocks started) or alternatively a call into the 
> targets when expansion is done.
> 
> I'm leaning towards the former.  Sorry I wasn't considering the problem 
> careful enough and thought the solution was obvious when it wasn't :-)

Looks like something like this could be useful to avoid code
duplications in the backends:

void
emit_insn_at_top (rtx insn)
{
  rtx scan;

  gcc_assert (current_ir_type () != IR_RTL_CFGLAYOUT);
  push_topmost_sequence ();
  scan = get_insns ();
  while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
    scan = NEXT_INSN (scan);

  emit_insn_after (insn, scan);
  pop_topmost_sequence ();
}

mips16_gp_pseudo_reg () in config/mips/mips.c is already using something
like that.

Paolo


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]