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Re: help for arm avr bfin cris frv h8300 m68k mcore mmix pdp11 rs6000 sh vax

From: Paolo Bonzini <bonzini at gnu dot org>
To: Michael Meissner <meissner at linux dot vnet dot ibm dot com>, Paolo Bonzini <bonzini at gnu dot org>, "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
Date: Fri, 13 Mar 2009 18:52:09 +0100
Subject: Re: help for arm avr bfin cris frv h8300 m68k mcore mmix pdp11 rs6000 sh vax
References: <f865508f0903130434i795ab1ck7c6d4e840951279@mail.gmail.com> <20090313155045.GA7711@hungry-tiger.westford.ibm.com>

> Note, one thing I encountered when doing the SSE5 work at AMD, is
> SHIFT_COUNT_TRUNCATED really needs a mode argument (and ideally should be moved
> into the gcc_target structure).

In fact I'm reusing the TARGET_SHIFT_TRUNCATION_MASK element that is
already there and accepts a mode.

Paolo

References:
- help for arm avr bfin cris frv h8300 m68k mcore mmix pdp11 rs6000 sh vax
  - From: Paolo Bonzini
- Re: help for arm avr bfin cris frv h8300 m68k mcore mmix pdp11 rs6000 sh vax
  - From: Michael Meissner

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