This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: help for arm avr bfin cris frv h8300 m68k mcore mmix pdp11 rs6000 sh vax
- From: Ian Lance Taylor <iant at google dot com>
- To: Paolo Bonzini <bonzini at gnu dot org>
- Cc: "gcc\ at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>, richard dot earnshaw at arm dot com, bernd dot schmidt at analog dot com, hp at axis dot com, aldyh at redhat dot com, aoliva at redhat dot com, law at redhat dot com, nickc at redhat dot com, kazu at codesourcery dot com, ni1d at arrl dot net, kkojima at gcc dot gnu dot org, matt at 3am-software dot com
- Date: Fri, 13 Mar 2009 06:12:25 -0700
- Subject: Re: help for arm avr bfin cris frv h8300 m68k mcore mmix pdp11 rs6000 sh vax
- References: <f865508f0903130434i795ab1ck7c6d4e840951279@mail.gmail.com>
Paolo Bonzini <bonzini@gnu.org> writes:
> This in turn means that the description given by SHIFT_COUNT_TRUNCATED
> must be exact. Right now !SHIFT_COUNT_TRUNCATED means "I don't know",
> I want it to mean "it is never truncated".
You need to do more work to make that happen, as SHIFT_COUNT_TRUNCATED
applies to both the shift instructions and the bitfield instructions.
On some processors one or the other is truncated; SHIFT_COUNT_TRUNCATED
may currently only be set to 1 if both are truncated. (E.g., I believe
that m68k truncates shifts but not bitfield instructions.)
Ian