RE: How to define 2 bypasses for a single pair of insn_reservation

["Ye, Joey" <joey dot ye at intel dot com>]

Maxim and Vladimir Wrote:
>>> Anyone can help me through this please?
>>>   
>> It was supposed to have two latency definitions at most (one in 
>> define_insn_reservation and another one in define_bypass).  That time it 
>> seemed enough for all processors supported by GCC.  It also simplified 
>> semantics definition when two bypass conditions returns true for the 
>> same insn pair.
>> 
>> If you really need more one bypass for insn pair, I could implement 
>> this.  Please, let me know.  In this case semantics of choosing latency 
>> time could be
>> 
>> o time in first bypass occurred in pipeline description whose condition 
>> returns true
>> o time given in define_insn_reservation
>
> I had a similar problem with ColdFire V4 scheduler model and the 
> solution for me was using adjust_cost() target hook; it is a bit 
> complicated, but it works fine.  Search m68k.c for 'bypass' for more 
> information, comments there describe the thing in sufficient detail.
Thanks Maxim and Vlad, I'd take a look at m68k.c before knowing it is really needed to extension the semantics.

Thanks - Joey