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Re: gcc-4.3.0/ppc32 inline assembly produces bad code

Andreas Schwab wrote:
Till Straumann <> writes:

/* Powerpc I/O barrier instruction */
#define EIEIO(pmem) do { asm volatile("eieio":"=m"(*pmem):"m"(*pmem)); }
while (0)

Looking closer, your asm statement has a bug. The "m" constraint can match memory addresses with side effects (auto inc/dec), but the insn does not carry out that side effect.
I'm sorry - that's a bit too brief for me to understand. Are you
talking about the memory-input or memory-output operand?
Could you please elaborate a little bit?

Also, did you look at my other example?

test(volatile unsigned *base)
  volatile unsigned *reg_p = base + IEVENT_REG/sizeof(*base);
  unsigned           val;

  /* tell gcc that the asm needs/looks at *reg_p */
  asm volatile ("lwz %0, 16(%1)":"=r"(val):"b"(base),"m"(*reg_p));

  while ( ! (val & IEVENT_GRSC) )
      val = *reg_p;

-- Till

  On powerpc the side effect must be
encoded through the update form of the load/store insns.  If you don't
use a load or store insn with the operand the you must use the "o"
constraint to avoid the side effect.


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