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Re: gcc-4.3.0/ppc32 inline assembly produces bad code

Daniel Jacobowitz <> writes:

> On Mon, Mar 31, 2008 at 11:19:29AM +0200, Andreas Schwab wrote:
>> Till Straumann <> writes:
>> > /* Powerpc I/O barrier instruction */
>> > #define EIEIO(pmem) do { asm volatile("eieio":"=m"(*pmem):"m"(*pmem)); }
>> > while (0)
>> Looking closer, your asm statement has a bug.  The "m" constraint can
>> match memory addresses with side effects (auto inc/dec), but the insn
>> does not carry out that side effect.  On powerpc the side effect must be
>> encoded through the update form of the load/store insns.  If you don't
>> use a load or store insn with the operand the you must use the "o"
>> constraint to avoid the side effect.
> Should asm "m" be required to carry out the side effect?

The side effect is carried out by using %U0, which expands to u for a
PRE_{INC,DEC,MODIFY} operand.  There is no way to encode that in the
insn operand itself, unlike m68k, for example.  The ia64 target has a
similar issue.


Andreas Schwab, SuSE Labs,
SuSE Linux Products GmbH, Maxfeldstraße 5, 90409 Nürnberg, Germany
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"And now for something completely different."

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