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Re: gcc-4.3.0/ppc32 inline assembly produces bad code
- From: Andreas Schwab <schwab at suse dot de>
- To: Till Straumann <strauman at slac dot stanford dot edu>
- Cc: gcc at gcc dot gnu dot org, RTEMS List <rtems-users at rtems dot com>
- Date: Mon, 31 Mar 2008 11:19:29 +0200
- Subject: Re: gcc-4.3.0/ppc32 inline assembly produces bad code
- References: <47EA78E1.2040100@slac.stanford.edu>
Till Straumann <strauman@slac.stanford.edu> writes:
> /* Powerpc I/O barrier instruction */
> #define EIEIO(pmem) do { asm volatile("eieio":"=m"(*pmem):"m"(*pmem)); }
> while (0)
Looking closer, your asm statement has a bug. The "m" constraint can
match memory addresses with side effects (auto inc/dec), but the insn
does not carry out that side effect. On powerpc the side effect must be
encoded through the update form of the load/store insns. If you don't
use a load or store insn with the operand the you must use the "o"
constraint to avoid the side effect.
Andreas.
--
Andreas Schwab, SuSE Labs, schwab@suse.de
SuSE Linux Products GmbH, Maxfeldstraße 5, 90409 Nürnberg, Germany
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