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Re: Test Harness and SPARC VIS Instructions

On Thu, Mar 13, 2008 at 11:31 AM, Joel Sherrill
<> wrote:
> Hi,
>  Moving on the SPARC, I see a lot of similar
>  unsupported instruction failures.  I only
>  see a single sparc feature test.  It is for
>  "-multrasparc -mvis" and it is actually
>  passing on the sparc instruction simulator in
>  gdb. It doesn't make me feel good that this
>  part passes since I thought SIS was a vanilla
>  V7 simulator. I think this test isn't tight enough:
>  proc check_effective_target_ultrasparc_hw { } {
>     return [check_runtime ultrasparc_hw {
>     int main() { return 0; }
>     } "-mcpu=ultrasparc"]
>  }
>  For sure though, SIS does NOT support VIS and
>  there is no test for that.  This leads to this:
>  Starting program:
>  /home/joel/work-gnat/svn/b-gcc1-sparc/gcc/testsuite/gcc/pr18400.exe
>  Unexpected trap (0x 2) at address 0x02001318
>  illegal instruction
>  Program exited normally.
>  (gdb) disassemble 0x02001318
>  Dump of assembler code for function check_vect:
>  ...
>  0x02001318 <check_vect+20>:     impdep1  62, %g0, %g0, %g0
>  ...
>  Can someone familiar with VIS provide an instruction
>  that is OK to do a run-time test with to check if
>  it is supported?

I don't think there's any user level instruction/register to do that.
You'll have to catch the illegal instruction trap :(


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