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Re: Redundant logical operations left after early splitting
- From: hutchinsonandy at aim dot com
- To: JeffLaw at aol dot com, "<law"@redhat.com><law at redhat dot com>, dave dot korn at artimi dot com, gcc at gcc dot gnu dot org
- Date: Tue, 19 Feb 2008 23:34:27 -0500
- Subject: Re: Redundant logical operations left after early splitting
RTL dumps for Combine pass and ASMCONS (last one before local-alloc)
COMBINE
;; Function f (f)
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
insn_cost 2: 4
insn_cost 6: 16
insn_cost 7: 12
insn_cost 8: 16
insn_cost 9: 16
insn_cost 10: 16
insn_cost 11: 16
insn_cost 12: 16
insn_cost 13: 16
insn_cost 14: 16
insn_cost 15: 16
insn_cost 35: 4
insn_cost 36: 4
insn_cost 37: 4
insn_cost 38: 4
insn_cost 26: 0
Failed to match this instruction:
(parallel [
(set (reg:SI 44)
(zero_extend:SI (mem:QI (plus:HI (reg:HI 24 r24 [ P ])
(const_int 1 [0x1])) [0 S1 A8])))
(set (reg/v/f:HI 42 [ P ])
(reg:HI 24 r24 [ P ]))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 44)
(zero_extend:SI (mem:QI (plus:HI (reg:HI 24 r24 [ P ])
(const_int 1 [0x1])) [0 S1 A8])))
(set (reg/v/f:HI 42 [ P ])
(reg:HI 24 r24 [ P ]))
])
Failed to match this instruction:
(set (reg:SI 45)
(ashift:SI (zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 1 [0x1])) [0 S1 A8]))
(const_int 24 [0x18])))
Failed to match this instruction:
(parallel [
(set (reg:SI 45)
(ashift:SI (zero_extend:SI (mem:QI (plus:HI (reg:HI 24 r24
[ P ])
(const_int 1 [0x1])) [0 S1 A8]))
(const_int 24 [0x18])))
(set (reg/v/f:HI 42 [ P ])
(reg:HI 24 r24 [ P ]))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 45)
(ashift:SI (zero_extend:SI (mem:QI (plus:HI (reg:HI 24 r24
[ P ])
(const_int 1 [0x1])) [0 S1 A8]))
(const_int 24 [0x18])))
(set (reg/v/f:HI 42 [ P ])
(reg:HI 24 r24 [ P ]))
])
Successfully matched this instruction:
(set (reg/v/f:HI 42 [ P ])
(reg:HI 24 r24 [ P ]))
Failed to match this instruction:
(set (reg:SI 45)
(ashift:SI (zero_extend:SI (mem:QI (plus:HI (reg:HI 24 r24 [ P ])
(const_int 1 [0x1])) [0 S1 A8]))
(const_int 24 [0x18])))
Failed to match this instruction:
(set (reg:SI 47)
(ashift:SI (zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 2 [0x2])) [0 S1 A8]))
(const_int 16 [0x10])))
Failed to match this instruction:
(set (reg:SI 48)
(ior:SI (ashift:SI (reg:SI 44)
(const_int 24 [0x18]))
(reg:SI 47)))
Failed to match this instruction:
(set (reg:SI 48)
(ior:SI (ashift:SI (reg:SI 46)
(const_int 16 [0x10]))
(reg:SI 45)))
Failed to match this instruction:
(set (reg:SI 48)
(ior:SI (ashift:SI (zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42
[ P ])
(const_int 1 [0x1])) [0 S1 A8]))
(const_int 24 [0x18]))
(reg:SI 47)))
Successfully matched this instruction:
(set (reg:SI 45)
(zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 1 [0x1])) [0 S1 A8])))
Failed to match this instruction:
(set (reg:SI 48)
(ior:SI (ashift:SI (reg:SI 45)
(const_int 24 [0x18]))
(reg:SI 47)))
Failed to match this instruction:
(set (reg:SI 48)
(ior:SI (ashift:SI (zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42
[ P ])
(const_int 2 [0x2])) [0 S1 A8]))
(const_int 16 [0x10]))
(reg:SI 45)))
Successfully matched this instruction:
(set (reg:SI 47)
(zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 2 [0x2])) [0 S1 A8])))
Failed to match this instruction:
(set (reg:SI 48)
(ior:SI (ashift:SI (reg:SI 47)
(const_int 16 [0x10]))
(reg:SI 45)))
Failed to match this instruction:
(set (reg:SI 48)
(ior:SI (ashift:SI (reg:SI 46)
(const_int 16 [0x10]))
(ashift:SI (reg:SI 44)
(const_int 24 [0x18]))))
Successfully matched this instruction:
(set (reg:SI 47)
(ashift:SI (reg:SI 44)
(const_int 24 [0x18])))
Failed to match this instruction:
(set (reg:SI 48)
(ior:SI (ashift:SI (reg:SI 46)
(const_int 16 [0x10]))
(reg:SI 47)))
Failed to match this instruction:
(set (reg:SI 50)
(ior:SI (ior:SI (reg:SI 45)
(reg:SI 47))
(reg:SI 49)))
Failed to match this instruction:
(set (reg:SI 50)
(ior:SI (zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 4 [0x4])) [0 S1 A8]))
(reg:SI 48)))
Failed to match this instruction:
(set (reg:SI 50)
(ior:SI (ior:SI (ashift:SI (reg:SI 44)
(const_int 24 [0x18]))
(reg:SI 47))
(reg:SI 49)))
Successfully matched this instruction:
(set (reg:SI 48)
(ashift:SI (reg:SI 44)
(const_int 24 [0x18])))
Failed to match this instruction:
(set (reg:SI 50)
(ior:SI (ior:SI (reg:SI 48)
(reg:SI 47))
(reg:SI 49)))
Failed to match this instruction:
(set (reg:SI 50)
(ior:SI (ior:SI (ashift:SI (reg:SI 46)
(const_int 16 [0x10]))
(reg:SI 45))
(reg:SI 49)))
Successfully matched this instruction:
(set (reg:SI 48)
(ashift:SI (reg:SI 46)
(const_int 16 [0x10])))
Failed to match this instruction:
(set (reg:SI 50)
(ior:SI (ior:SI (reg:SI 48)
(reg:SI 45))
(reg:SI 49)))
Failed to match this instruction:
(set (reg:SI 50)
(ior:SI (ior:SI (zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P
])
(const_int 4 [0x4])) [0 S1 A8]))
(reg:SI 45))
(reg:SI 47)))
Successfully matched this instruction:
(set (reg:SI 49)
(zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 4 [0x4])) [0 S1 A8])))
Failed to match this instruction:
(set (reg:SI 50)
(ior:SI (ior:SI (reg:SI 49)
(reg:SI 45))
(reg:SI 47)))
Failed to match this instruction:
(set (reg:SI 52)
(ashift:SI (zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 3 [0x3])) [0 S1 A8]))
(const_int 8 [0x8])))
Failed to match this instruction:
(set (reg:SI 43)
(ior:SI (ior:SI (reg:SI 48)
(reg:SI 49))
(reg:SI 52)))
Failed to match this instruction:
(set (reg:SI 43)
(ior:SI (ashift:SI (reg:SI 51)
(const_int 8 [0x8]))
(reg:SI 50)))
Failed to match this instruction:
(set (reg:SI 43)
(ior:SI (ior:SI (ior:SI (reg:SI 45)
(reg:SI 47))
(reg:SI 49))
(reg:SI 52)))
Successfully matched this instruction:
(set (reg:SI 50)
(ior:SI (reg:SI 45)
(reg:SI 47)))
Failed to match this instruction:
(set (reg:SI 43)
(ior:SI (ior:SI (reg:SI 50)
(reg:SI 49))
(reg:SI 52)))
Failed to match this instruction:
(set (reg:SI 43)
(ior:SI (ior:SI (zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P
])
(const_int 4 [0x4])) [0 S1 A8]))
(reg:SI 48))
(reg:SI 52)))
Successfully matched this instruction:
(set (reg:SI 50)
(zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 4 [0x4])) [0 S1 A8])))
Failed to match this instruction:
(set (reg:SI 43)
(ior:SI (ior:SI (reg:SI 50)
(reg:SI 48))
(reg:SI 52)))
Failed to match this instruction:
(set (reg:SI 43)
(ior:SI (ashift:SI (zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42
[ P ])
(const_int 3 [0x3])) [0 S1 A8]))
(const_int 8 [0x8]))
(reg:SI 50)))
Successfully matched this instruction:
(set (reg:SI 52)
(zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 3 [0x3])) [0 S1 A8])))
Failed to match this instruction:
(set (reg:SI 43)
(ior:SI (ashift:SI (reg:SI 52)
(const_int 8 [0x8]))
(reg:SI 50)))
Failed to match this instruction:
(set (reg:SI 43)
(ior:SI (ior:SI (ashift:SI (reg:SI 51)
(const_int 8 [0x8]))
(reg:SI 48))
(reg:SI 49)))
Successfully matched this instruction:
(set (reg:SI 52)
(ashift:SI (reg:SI 51)
(const_int 8 [0x8])))
Failed to match this instruction:
(set (reg:SI 43)
(ior:SI (ior:SI (reg:SI 52)
(reg:SI 48))
(reg:SI 49)))
f
Dataflow summary:
;; invalidated by call 0 [r0] 1 [r1] 18 [r18] 19 [r19] 20 [r20]
21 [r21] 22 [r22] 23 [r23] 24 [r24] 25 [r25] 26 [r26] 27 [r27] 30 [r30]
31 [r31] 33 [__SP_H__] 35 [argH]
;; hardware regs used 28 [r28] 32 [__SP_L__] 34 [argL]
;; regular block artificial uses 28 [r28] 32 [__SP_L__] 34 [argL]
;; eh block artificial uses 28 [r28] 32 [__SP_L__] 34 [argL]
;; entry block defs 2 [r2] 8 [r8] 9 [r9] 10 [r10] 11 [r11] 12
[r12] 13 [r13] 14 [r14] 15 [r15] 16 [r16] 17 [r17] 18 [r18] 19 [r19] 20
[r20] 21 [r21] 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32
[__SP_L__] 34 [argL]
;; exit block uses 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28]
32 [__SP_L__]
;; regs ever live 22[r22] 23[r23] 24[r24] 25[r25]
(note 1 0 4 NOTE_INSN_DELETED)
;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(28){ }u1(32){ }u2(34){ }}
;; lr in 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; lr use 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; lr def 22 [r22] 23 [r23] 24 [r24] 25 [r25] 42 43 44 45 46 47
48 49 50 51 52
;; live in 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; live gen 22 [r22] 23 [r23] 24 [r24] 25 [r25] 42 43 44 45 46 47
48 49 50 51 52
;; live kill
;; Pred edge ENTRY [100.0%] (fallthru)
(note 4 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 2 4 3 2 tests.c:10 (set (reg/v/f:HI 42 [ P ])
(reg:HI 24 r24 [ P ])) 8 {*movhi} (expr_list:REG_DEAD (reg:HI
24 r24 [ P ])
(nil)))
(note 3 2 6 2 NOTE_INSN_FUNCTION_BEG)
(insn 6 3 7 2 tests.c:10 (set (reg:SI 44)
(zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 1 [0x1])) [0 S1 A8]))) 55
{zero_extendqisi2} (nil))
(insn 7 6 8 2 tests.c:10 (set (reg:SI 45)
(ashift:SI (reg:SI 44)
(const_int 24 [0x18]))) 61 {ashlsi3_const2p}
(expr_list:REG_DEAD (reg:SI 44)
(nil)))
(insn 8 7 9 2 tests.c:10 (set (reg:SI 46)
(zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 2 [0x2])) [0 S1 A8]))) 55
{zero_extendqisi2} (nil))
(insn 9 8 10 2 tests.c:10 (set (reg:SI 47)
(ashift:SI (reg:SI 46)
(const_int 16 [0x10]))) 61 {ashlsi3_const2p}
(expr_list:REG_DEAD (reg:SI 46)
(nil)))
(insn 10 9 11 2 tests.c:10 (set (reg:SI 48)
(ior:SI (reg:SI 45)
(reg:SI 47))) 46 {iorsi3} (expr_list:REG_DEAD (reg:SI 47)
(expr_list:REG_DEAD (reg:SI 45)
(nil))))
(insn 11 10 12 2 tests.c:10 (set (reg:SI 49)
(zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 4 [0x4])) [0 S1 A8]))) 55
{zero_extendqisi2} (nil))
(insn 12 11 13 2 tests.c:10 (set (reg:SI 50)
(ior:SI (reg:SI 48)
(reg:SI 49))) 46 {iorsi3} (expr_list:REG_DEAD (reg:SI 49)
(expr_list:REG_DEAD (reg:SI 48)
(nil))))
(insn 13 12 14 2 tests.c:10 (set (reg:SI 51)
(zero_extend:SI (mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 3 [0x3])) [0 S1 A8]))) 55
{zero_extendqisi2} (expr_list:REG_DEAD (reg/v/f:HI 42 [ P ])
(nil)))
(insn 14 13 15 2 tests.c:10 (set (reg:SI 52)
(ashift:SI (reg:SI 51)
(const_int 8 [0x8]))) 61 {ashlsi3_const2p}
(expr_list:REG_DEAD (reg:SI 51)
(nil)))
(insn 15 14 35 2 tests.c:10 (set (reg:SI 43)
(ior:SI (reg:SI 50)
(reg:SI 52))) 46 {iorsi3} (expr_list:REG_DEAD (reg:SI 52)
(expr_list:REG_DEAD (reg:SI 50)
(nil))))
(insn 35 15 36 2 tests.c:17 (set (reg:QI 22 r22 [ <result> ])
(subreg:QI (reg:SI 43) 0)) 4 {*movqi} (nil))
(insn 36 35 37 2 tests.c:17 (set (reg:QI 23 r23 [+1 ])
(subreg:QI (reg:SI 43) 1)) 4 {*movqi} (nil))
(insn 37 36 38 2 tests.c:17 (set (reg:QI 24 r24 [+2 ])
(subreg:QI (reg:SI 43) 2)) 4 {*movqi} (nil))
(insn 38 37 26 2 tests.c:17 (set (reg:QI 25 r25 [+3 ])
(subreg:QI (reg:SI 43) 3)) 4 {*movqi} (expr_list:REG_DEAD
(reg:SI 43)
(nil)))
(insn 26 38 0 2 tests.c:17 (use (reg/i:SI 22 r22)) -1 (nil))
;; End of basic block 2 -> ( 1)
;; lr out 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32
[__SP_L__] 34 [argL]
;; live out 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32
[__SP_L__] 34 [argL]
;; Succ edge EXIT [100.0%] (fallthru)
starting the processing of deferred insns
ending the processing of deferred insns
;; Combiner totals: 24 attempts, 24 substitutions (2 requiring new
space),
;; 0 successes.
ASMCONS (last one before local-alloc)
;; Function f (f)
f
Dataflow summary:
;; invalidated by call 0 [r0] 1 [r1] 18 [r18] 19 [r19] 20 [r20]
21 [r21] 22 [r22] 23 [r23] 24 [r24] 25 [r25] 26 [r26] 27 [r27] 30 [r30]
31 [r31] 33 [__SP_H__] 35 [argH]
;; hardware regs used 28 [r28] 32 [__SP_L__] 34 [argL]
;; regular block artificial uses 28 [r28] 32 [__SP_L__] 34 [argL]
;; eh block artificial uses 28 [r28] 32 [__SP_L__] 34 [argL]
;; entry block defs 2 [r2] 8 [r8] 9 [r9] 10 [r10] 11 [r11] 12
[r12] 13 [r13] 14 [r14] 15 [r15] 16 [r16] 17 [r17] 18 [r18] 19 [r19] 20
[r20] 21 [r21] 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32
[__SP_L__] 34 [argL]
;; exit block uses 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28]
32 [__SP_L__]
;; regs ever live 22[r22] 23[r23] 24[r24] 25[r25]
(note 1 0 4 NOTE_INSN_DELETED)
;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(28){ }u1(32){ }u2(34){ }}
;; lr in 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; lr use 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; lr def 22 [r22] 23 [r23] 24 [r24] 25 [r25] 42 43 44 45 46 47
48 49 50 51 52
;; live in 24 [r24] 25 [r25] 28 [r28] 32 [__SP_L__] 34 [argL]
;; live gen 22 [r22] 23 [r23] 24 [r24] 25 [r25] 42 43 44 45 46 47
48 49 50 51 52
;; live kill
;; Pred edge ENTRY [100.0%] (fallthru)
(note 4 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 2 4 3 2 tests.c:10 (set (reg/v/f:HI 42 [ P ])
(reg:HI 24 r24 [ P ])) 8 {*movhi} (expr_list:REG_DEAD (reg:HI
24 r24 [ P ])
(nil)))
(note 3 2 39 2 NOTE_INSN_FUNCTION_BEG)
(insn 39 3 40 2 tests.c:10 (set (reg:QI 62)
(mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 1 [0x1])) [0 S1 A8])) 4 {*movqi} (nil))
(insn 40 39 41 2 tests.c:10 (set (reg:QI 63 [+1 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 41 40 42 2 tests.c:10 (set (reg:QI 64 [+2 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 42 41 43 2 tests.c:10 (set (reg:QI 65 [+3 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 43 42 44 2 tests.c:10 (set (reg:QI 61 [+3 ])
(reg:QI 62)) 4 {*movqi} (nil))
(insn 44 43 45 2 tests.c:10 (set (reg:QI 58)
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 45 44 46 2 tests.c:10 (set (reg:QI 59 [+1 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 46 45 47 2 tests.c:10 (set (reg:QI 60 [+2 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 47 46 48 2 tests.c:10 (const_int 0 [0x0]) 110 {nop} (nil))
(insn 48 47 49 2 tests.c:10 (set (reg:QI 66)
(mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 2 [0x2])) [0 S1 A8])) 4 {*movqi} (nil))
(insn 49 48 50 2 tests.c:10 (set (reg:QI 67 [+1 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 50 49 51 2 tests.c:10 (set (reg:QI 68 [+2 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 51 50 52 2 tests.c:10 (set (reg:QI 69 [+3 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 52 51 53 2 tests.c:10 (set (reg:QI 72 [+2 ])
(reg:QI 66)) 4 {*movqi} (nil))
(insn 53 52 54 2 tests.c:10 (set (reg:QI 73 [+3 ])
(reg:QI 67 [+1 ])) 4 {*movqi} (nil))
(insn 54 53 55 2 tests.c:10 (set (reg:QI 70)
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 55 54 56 2 tests.c:10 (set (reg:QI 71 [+1 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 56 55 57 2 tests.c:10 (const_int 0 [0x0]) 110 {nop} (nil))
(insn 57 56 58 2 tests.c:10 (set (reg:QI 58)
(ior:QI (reg:QI 58)
(reg:QI 70))) 63 {iorqi3} (nil))
(insn 58 57 59 2 tests.c:10 (set (reg:QI 59 [+1 ])
(ior:QI (reg:QI 59 [+1 ])
(reg:QI 71 [+1 ]))) 63 {iorqi3} (nil))
(insn 59 58 60 2 tests.c:10 (set (reg:QI 60 [+2 ])
(ior:QI (reg:QI 60 [+2 ])
(reg:QI 72 [+2 ]))) 63 {iorqi3} (nil))
(insn 60 59 61 2 tests.c:10 (set (reg:QI 61 [+3 ])
(ior:QI (reg:QI 61 [+3 ])
(reg:QI 73 [+3 ]))) 63 {iorqi3} (nil))
(insn 61 60 62 2 tests.c:10 (set (reg:QI 74)
(mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 4 [0x4])) [0 S1 A8])) 4 {*movqi} (nil))
(insn 62 61 63 2 tests.c:10 (set (reg:QI 75 [+1 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 63 62 64 2 tests.c:10 (set (reg:QI 76 [+2 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 64 63 65 2 tests.c:10 (set (reg:QI 77 [+3 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 65 64 66 2 tests.c:10 (set (reg:QI 58)
(ior:QI (reg:QI 58)
(reg:QI 74))) 63 {iorqi3} (nil))
(insn 66 65 67 2 tests.c:10 (set (reg:QI 59 [+1 ])
(ior:QI (reg:QI 59 [+1 ])
(reg:QI 75 [+1 ]))) 63 {iorqi3} (nil))
(insn 67 66 68 2 tests.c:10 (set (reg:QI 60 [+2 ])
(ior:QI (reg:QI 60 [+2 ])
(reg:QI 76 [+2 ]))) 63 {iorqi3} (nil))
(insn 68 67 69 2 tests.c:10 (set (reg:QI 61 [+3 ])
(ior:QI (reg:QI 61 [+3 ])
(reg:QI 77 [+3 ]))) 63 {iorqi3} (nil))
(insn 69 68 70 2 tests.c:10 (set (reg:QI 78)
(mem:QI (plus:HI (reg/v/f:HI 42 [ P ])
(const_int 3 [0x3])) [0 S1 A8])) 4 {*movqi} (nil))
(insn 70 69 71 2 tests.c:10 (set (reg:QI 79 [+1 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 71 70 72 2 tests.c:10 (set (reg:QI 80 [+2 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 72 71 73 2 tests.c:10 (set (reg:QI 81 [+3 ])
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 73 72 74 2 tests.c:10 (set (reg:QI 83 [+1 ])
(reg:QI 78)) 4 {*movqi} (nil))
(insn 74 73 75 2 tests.c:10 (set (reg:QI 84 [+2 ])
(reg:QI 79 [+1 ])) 4 {*movqi} (nil))
(insn 75 74 76 2 tests.c:10 (set (reg:QI 85 [+3 ])
(reg:QI 80 [+2 ])) 4 {*movqi} (nil))
(insn 76 75 77 2 tests.c:10 (set (reg:QI 82)
(const_int 0 [0x0])) 4 {*movqi} (nil))
(insn 77 76 78 2 tests.c:10 (const_int 0 [0x0]) 110 {nop} (nil))
(insn 78 77 79 2 tests.c:10 (set (reg:QI 58)
(ior:QI (reg:QI 58)
(reg:QI 82))) 63 {iorqi3} (nil))
(insn 79 78 80 2 tests.c:10 (set (reg:QI 59 [+1 ])
(ior:QI (reg:QI 59 [+1 ])
(reg:QI 83 [+1 ]))) 63 {iorqi3} (nil))
(insn 80 79 81 2 tests.c:10 (set (reg:QI 60 [+2 ])
(ior:QI (reg:QI 60 [+2 ])
(reg:QI 84 [+2 ]))) 63 {iorqi3} (nil))
(insn 81 80 35 2 tests.c:10 (set (reg:QI 61 [+3 ])
(ior:QI (reg:QI 61 [+3 ])
(reg:QI 85 [+3 ]))) 63 {iorqi3} (nil))
(insn 35 81 36 2 tests.c:17 (set (reg:QI 22 r22 [ <result> ])
(reg:QI 58)) 4 {*movqi} (nil))
(insn 36 35 37 2 tests.c:17 (set (reg:QI 23 r23 [+1 ])
(reg:QI 59 [+1 ])) 4 {*movqi} (nil))
(insn 37 36 38 2 tests.c:17 (set (reg:QI 24 r24 [+2 ])
(reg:QI 60 [+2 ])) 4 {*movqi} (nil))
(insn 38 37 26 2 tests.c:17 (set (reg:QI 25 r25 [+3 ])
(reg:QI 61 [+3 ])) 4 {*movqi} (nil))
(insn 26 38 0 2 tests.c:17 (use (reg/i:SI 22 r22)) -1 (nil))
;; End of basic block 2 -> ( 1)
;; lr out 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32
[__SP_L__] 34 [argL]
;; live out 22 [r22] 23 [r23] 24 [r24] 25 [r25] 28 [r28] 32
[__SP_L__] 34 [argL]
;; Succ edge EXIT [100.0%] (fallthru)
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