Segmented Register file Implementation

["Balaji V. Iyer" <bviyer at ncsu dot edu>]

Hello Everyone,
	I am currently working on dividing the register file into two
different processing element. In the first processing element (PE) I
want to have certain operations (add, sub, mult, div, branch,
jumps..etc) in first PE and loads and stores should be in the 2nd
Processing Element. A couple specialized instructions were created to
copy data between PEs. Also, both the processing elements are able to
process add instructions. I want to put Registers 0-15 to PE#1 and 16-31
to PE#2. I am currently using OpenRISC Port of GCC (4.0.2). 

	I have modified the machine description and assigned the PE#1
operations to register class "a" and the operations for PE#2 to register
class "b." Also I have set these letters appropriately in the or32.h
file.

	Now, my question is this: How can I make the register allocator
allocate correctly based on the restrictions I have set?

	Secondly, let's say I want to go through the instruction list
(mostly in the machine_dependent_reorg function) and want certain ADDs
to be put in a specific PE. This is mainly done to reduce the number of
inter-PE copies. Is there a way I can set a certain flag (or create a
certain FLAG) on the instruction (I know instruction is an RTX
structure) so that the register allocator can recognize this?
 

Any help is greatly appreciated.

Yours Sincerely,

Balaji V. Iyer.

-- 
 
Balaji V. Iyer
PhD Student, 
Center for Efficient, Scalable and Reliable Computing,
Department of Electrical and Computer Engineering,
North Carolina State University.