Register allocation issues

["Matt Lee" <reachmatt dot lee at gmail dot com>]

Hello,

On my simple RISC architecture I am seeing suboptimal instruction
scheduling with GCC-4.1.1 caused by the way registers are getting
allocated. I am looking for suggestions on what could be wrong in my
description to cause the poor allocation.

More details --

Registers r3 to r12 are volatiles. However, for the C code below,

struct foo {
    int a[4];
} ;

struct foo p, q;

void func ()
{
    memcpy (&p, &q, sizeof (struct foo));
}

I am getting a instruction sequence for func() such as,

load r3, q + 0
load r4, q + 4
store r3, p + 0
store r4, p + 4
load r3, q + 4
load r4, q + 8
store r3, p + 4
store r4, p + 8

The problem is, that though the loads can be optimized by pipelining
them. The register allocator has created a dependency by using only r3
and r4, instead of using the other volatiles.

Strangely, modifying func to the following helps,

void func (struct foo *p, struct foo *q)
{
    memcpy (p, q, sizeof (struct foo));
}

Now the register allocator uses more volatile registers and there are
no false dependencies.

I have attached the header information from the .lreg file for the
poor register allocation case. Pseudos 87 and 88 get assigned again to
r3, r4 instead of new volatiles.

Is this a problem with some poor cost model in my backend? How do I
get more information  about why the register allocator didn't pick the
other volatiles?

-- 
thanks,
Matt

Attachment: func.lreg
Description: Binary data