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Re: reload question
Pat Haugen <pthaugen@us.ibm.com> writes:
> I'm looking into a few cases where we're still getting the base/index
> operand ordering wrong on PowerPC for an indexed load/store instruction,
> even after the PTR_PLUS merge and fix for PR28690. One of the cases I
> observed was caused by reload picking r0 to use for the base reg opnd as a
> result of spilling. Since r0 is not a valid register for the base reg
> position, we end up switching the order of the operands before emitting the
> instruction which then causes the performance hit on Power6. r0 is not a
> valid BASE_REG_CLASS register, only INDEX_REG_CLASS, but the following
> section of code from reload.c:find_reloads_address_1() dealing with
> PLUS(REG REG) may try assigning the base reg opnd to the INDEX_REG class in
> a couple situations. This then allows r0 to be picked for the base reg
> opnd. Is this being done on purpose (going on assumption that operands are
> commutative), such as to allow more opportunities for a successful
> allocation with reduced spill? If it's not wise for me to modify this
> code, possibly due to effect on other architectures, what are some other
> options (maybe introduce a new HONOR_BASE_INDEX_ORDER target macro)?
I'm not entirely clear: how do you propose changing the code?
Ian