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Re: m68k bootstrap problem


Roman Zippel wrote:
> Hi,
>
> m68k currently doesn't bootstrap, which I think is dataflow related, the 
> whole precompiled file is at http://www.xs4all.nl/~zippel/expmed.i.gz, but 
> the small test below should be enough to demonstrate the problem 
> (although it doesn't crash):
>
> int fi1(int);
> int fi2(int);
> void *fp1(int, void *);
> void *fp2(int, int);
>
> void *f(int x, int a, int b)
> {
>         if (x) {
>                 int y = fi1(1);
>                 void *p;
>                 y += fi2(3);
>                 p = fp1(2, 0);
>                 return fp1(y, p);
>         } else {
>                 int z = fi2(2);
>                 z += fi1(z);
>                 return fp2(z, 3);
>         }
> }
>
> The function is exited here via a sibcall, one important thing is that 
> current_function_return_rtx is set to:
>
> (parallel/i:SI [
>         (expr_list:REG_DEP_TRUE (reg:SI 8 %a0 [ <result> ])
>             (const_int 0 [0x0]))
>         (expr_list:REG_DEP_TRUE (reg:SI 0 %d0 [ <result> ])
>             (const_int 0 [0x0]))
>     ])
>
> This means the return value is returned in both %d0/%a0.
>
> The problem is now that this seems to produce incorrect REG_DEAD notes for 
> %d0, they are missing at the last use before the sibcall. This now seems 
> to confuse reload in the full test case, where it calls 
> save_call_clobbered_regs(), which can't quite decide whether to save %d0 
> across a function call or not.
> setup_save_areas() doesn't create a stack slot for %d0 because it's not 
> associated with a pseudo which lives across a function call, but later in 
> save_call_clobbered_regs() %d0 is still live at a function call and it
> attempts to save the register, which fails due to the missing stack slot.
>
> AFAICT this behaviour is correct, the question is now how do I get 
> correct REG_DEAD notes? It seems to be related to the unusual return 
> expression above, but at this point I need some help to fix this.
>
> bye, Roman
>   
a particularly useful kind of debugging is available for these kinds of
problems.
if you change the 0 to a 1 at df-problems.c:49, it will turn on a
verbose trace of the process that it goes thru to decide to build
reg_dead notes.  This process includes listing all of the info for each
of the insn's uses and defs. 

The reason that there is no reg_dead not in the last use (insn 45)
before the sib_call (insn 46)  is that there is no def for r0 in the
sibcall (insn 46) and r0 is live at the end of the block.

This of course changes the question to not why there no note to why is
there no def.

Kenny


;; Function f (f)

starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called


f

Dataflow summary:
def_info->table_size = 68, use_info->table_size = 52
;;  invalidated by call 	 0 [%d0] 1 [%d1] 8 [%a0] 9 [%a1] 16 [%fp0] 17 [%fp1]
;;  hardware regs used 	 14 [%a6] 15 [%sp] 24 [%argptr]
;;  regular block artificial uses 	 14 [%a6] 15 [%sp] 24 [%argptr]
;;  eh block artificial uses 	 14 [%a6] 15 [%sp] 24 [%argptr]
;;  entry block defs 	 8 [%a0] 9 [%a1] 14 [%a6] 15 [%sp] 24 [%argptr]
;;  exit block uses 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp]
;;  regs ever live 	 0[%d0] 8[%a0] 15[%sp]
(note 1 0 6)

;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(14){ }u1(15){ }u2(24){ }}
;; lr  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  use 	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  def 	
;; urec  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  gen 	
;; urec  kill	
;; urec  ec	

;; Pred edge  ENTRY [100.0%]  (fallthru)
(note 6 1 2 2 [bb 2])

(note 2 6 5 2)

(note 5 2 8 2)

(insn:QI 8 5 9 2 test.c:8 (set (cc0)
        (mem/c/i:SI (plus:SI (reg/f:SI 24 %argptr)
                (const_int 8 [0x8])) [3 x+0 S4 A32])) 3 {*m68k.md:221} (nil))

(jump_insn 9 8 10 2 test.c:8 (set (pc)
        (if_then_else (eq (cc0)
                (const_int 0 [0x0]))
            (label_ref 32)
            (pc))) 386 {beq} (expr_list:REG_BR_PROB (const_int 5400 [0x1518])
        (nil)))
;; End of basic block 2 -> ( 3 4)
;; lr  out 	 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  out 	 14 [%a6] 15 [%sp] 24 [%argptr]


;; Succ edge  3 [46.0%]  (fallthru)
;; Succ edge  4 [54.0%] 

;; Start of basic block ( 2) -> 3
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u5(14){ }u6(15){ }u7(24){ }}
;; lr  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  use 	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  def 	 0 [%d0] 1 [%d1] 8 [%a0] 9 [%a1] 15 [%sp] 16 [%fp0] 17 [%fp1] 32 35
;; urec  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  gen 	 0 [%d0] 8 [%a0] 15 [%sp] 32 35
;; urec  kill	 0 [%d0] 8 [%a0] 15 [%sp] 32 35
;; urec  ec	

;; Pred edge  2 [46.0%]  (fallthru)
(note 10 9 11 3 [bb 3])

(insn 11 10 12 3 test.c:9 (set (mem/i:SI (pre_dec:SI (reg/f:SI 15 %sp)) [0 S4 A16])
        (const_int 1 [0x1])) 29 {pushexthisi_const} (nil))

(note 12 11 13 3)

(call_insn 13 12 14 3 test.c:9 (set (reg:SI 0 %d0)
        (call (mem:QI (symbol_ref:SI ("fi1") [flags 0x41] <function_decl 0x2b6e5d2b4700 fi1>) [0 S1 A8])
            (const_int 4 [0x4]))) 432 {*call_value} (nil)
    (nil))

(insn 14 13 15 3 test.c:9 (set (reg/v:SI 32 [ y ])
        (reg:SI 0 %d0)) 31 {*m68k.md:679} (expr_list:REG_DEAD (reg:SI 0 %d0)
        (nil)))

(insn 15 14 16 3 test.c:11 (set (mem/i:SI (pre_dec:SI (reg/f:SI 15 %sp)) [0 S4 A16])
        (const_int 3 [0x3])) 29 {pushexthisi_const} (nil))

(note 16 15 17 3)

(call_insn 17 16 18 3 test.c:11 (set (reg:SI 0 %d0)
        (call (mem:QI (symbol_ref:SI ("fi2") [flags 0x41] <function_decl 0x2b6e5d2b4800 fi2>) [0 S1 A8])
            (const_int 4 [0x4]))) 432 {*call_value} (nil)
    (nil))

(insn 18 17 19 3 test.c:11 (set (reg:SI 35 [ D.1588 ])
        (reg:SI 0 %d0)) 31 {*m68k.md:679} (nil))

(insn 19 18 20 3 test.c:12 (set (mem/f/i:SI (pre_dec:SI (reg/f:SI 15 %sp)) [0 S4 A16])
        (const_int 0 [0x0])) 29 {pushexthisi_const} (nil))

(insn 20 19 21 3 test.c:12 (set (mem/i:SI (pre_dec:SI (reg/f:SI 15 %sp)) [0 S4 A16])
        (const_int 2 [0x2])) 29 {pushexthisi_const} (nil))

(note 21 20 22 3)

(call_insn 22 21 23 3 test.c:12 (set (reg:SI 8 %a0)
        (call (mem:QI (symbol_ref:SI ("fp1") [flags 0x41] <function_decl 0x2b6e5d2b4900 fp1>) [0 S1 A8])
            (const_int 8 [0x8]))) 432 {*call_value} (nil)
    (nil))

(note 23 22 24 3)

(insn 24 23 25 3 test.c:13 (set (reg/f:SI 15 %sp)
        (plus:SI (reg/f:SI 15 %sp)
            (const_int 16 [0x10]))) 127 {*addsi3_internal} (nil))

(insn 25 24 26 3 test.c:13 (set (mem:SI (plus:SI (reg/f:SI 24 %argptr)
                (const_int 12 [0xc])) [0 S4 A32])
        (reg:SI 8 %a0)) 31 {*m68k.md:679} (expr_list:REG_DEAD (reg:SI 8 %a0)
        (nil)))

(note 26 25 27 3)

(insn 27 26 28 3 test.c:13 (set (mem:SI (plus:SI (reg/f:SI 24 %argptr)
                (const_int 8 [0x8])) [0 S4 A32])
        (plus:SI (reg:SI 35 [ D.1588 ])
            (reg/v:SI 32 [ y ]))) 127 {*addsi3_internal} (expr_list:REG_DEAD (reg:SI 35 [ D.1588 ])
        (expr_list:REG_DEAD (reg/v:SI 32 [ y ])
            (nil))))

(call_insn/j 28 27 29 3 test.c:13 (set (reg:SI 8 %a0)
        (call (mem:QI (symbol_ref:SI ("fp1") [flags 0x41] <function_decl 0x2b6e5d2b4900 fp1>) [0 S1 A8])
            (const_int 8 [0x8]))) 430 {*sibcall_value} (nil)
    (nil))
;; End of basic block 3 -> ( 1)
;; lr  out 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  out 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]


;; Succ edge  EXIT [100.0%]  (ab,sibcall)

(barrier 29 28 32)

;; Start of basic block ( 2) -> 4
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u29(14){ }u30(15){ }u31(24){ }}
;; lr  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  use 	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  def 	 0 [%d0] 1 [%d1] 8 [%a0] 9 [%a1] 15 [%sp] 16 [%fp0] 17 [%fp1] 30
;; urec  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  gen 	 0 [%d0] 8 [%a0] 15 [%sp] 30
;; urec  kill	 0 [%d0] 8 [%a0] 15 [%sp] 30
;; urec  ec	

;; Pred edge  2 [54.0%] 
(code_label 32 29 33 4 2 "" [1 uses])

(note 33 32 34 4 [bb 4])

(insn 34 33 35 4 test.c:15 (set (mem/i:SI (pre_dec:SI (reg/f:SI 15 %sp)) [0 S4 A16])
        (const_int 2 [0x2])) 29 {pushexthisi_const} (nil))

(note 35 34 36 4)

(call_insn 36 35 37 4 test.c:15 (set (reg:SI 0 %d0)
        (call (mem:QI (symbol_ref:SI ("fi2") [flags 0x41] <function_decl 0x2b6e5d2b4800 fi2>) [0 S1 A8])
            (const_int 4 [0x4]))) 432 {*call_value} (nil)
    (nil))

(insn 37 36 38 4 test.c:15 (set (reg/v:SI 30 [ z ])
        (reg:SI 0 %d0)) 31 {*m68k.md:679} (expr_list:REG_DEAD (reg:SI 0 %d0)
        (nil)))

(insn 38 37 39 4 test.c:16 (set (mem/i:SI (pre_dec:SI (reg/f:SI 15 %sp)) [0 S4 A16])
        (reg/v:SI 30 [ z ])) 31 {*m68k.md:679} (nil))

(note 39 38 40 4)

(call_insn 40 39 41 4 test.c:16 (set (reg:SI 0 %d0)
        (call (mem:QI (symbol_ref:SI ("fi1") [flags 0x41] <function_decl 0x2b6e5d2b4700 fi1>) [0 S1 A8])
            (const_int 4 [0x4]))) 432 {*call_value} (nil)
    (nil))

(note 41 40 42 4)

(insn 42 41 43 4 test.c:17 (set (reg/f:SI 15 %sp)
        (plus:SI (reg/f:SI 15 %sp)
            (const_int 8 [0x8]))) 127 {*addsi3_internal} (nil))

(insn 43 42 44 4 test.c:17 (set (mem:SI (plus:SI (reg/f:SI 24 %argptr)
                (const_int 12 [0xc])) [0 S4 A32])
        (const_int 3 [0x3])) 31 {*m68k.md:679} (nil))

(note 44 43 45 4)

(insn 45 44 46 4 test.c:17 (set (mem:SI (plus:SI (reg/f:SI 24 %argptr)
                (const_int 8 [0x8])) [0 S4 A32])
        (plus:SI (reg:SI 0 %d0)
            (reg/v:SI 30 [ z ]))) 127 {*addsi3_internal} (expr_list:REG_DEAD (reg/v:SI 30 [ z ])
        (nil)))

(call_insn/j 46 45 47 4 test.c:17 (set (reg:SI 8 %a0)
        (call (mem:QI (symbol_ref:SI ("fp2") [flags 0x41] <function_decl 0x2b6e5d2b4a00 fp2>) [0 S1 A8])
            (const_int 8 [0x8]))) 430 {*sibcall_value} (nil)
    (nil))
;; End of basic block 4 -> ( 1)
;; lr  out 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  out 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]


;; Succ edge  EXIT [100.0%]  (ab,sibcall)

(barrier 47 46 0)

live at bottom  14 [%a6] 15 [%sp] 24 [%argptr]
artificial def 8
artificial def 9
artificial def 14
artificial def 15
artificial def 24
live before artificials out 
live at bottom 
live before artificials out  0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp]
live at bottom  14 [%a6] 15 [%sp] 24 [%argptr]
live before artificials out  14 [%a6] 15 [%sp] 24 [%argptr]
  regular looking at use u-1 reg 24 bb 2 insn 8 flag 0x0 type 0x2 loc 0x2b6e5d2d1b28(0x2b6e5c985040) chain { }
live at bottom  0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]
live before artificials out  0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]
processing call 28
  live = 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]
  regular looking at def d17 reg 8 bb 3 insn 28 flag 0x800 type 0x0 loc 0x2b6e5d2d1248(0x2b6e5d2d10a0) chain { }
  regular looking at use u28 reg 15 bb 3 insn 28 flag 0xa00 type 0x1 chain { }
deleting:  27 (expr_list:REG_DEAD (reg:SI 35 [ D.1588 ])
    (expr_list:REG_DEAD (reg/v:SI 32 [ y ])
        (nil)))
deleting:  27 (expr_list:REG_DEAD (reg/v:SI 32 [ y ])
    (nil))
  regular looking at use u-1 reg 24 bb 3 insn 27 flag 0x0 type 0x3 loc 0x2b6e5d2d1c88(0x2b6e5c985040) chain { }
  regular looking at use u-1 reg 32 bb 3 insn 27 flag 0x0 type 0x1 loc 0x2b6e5d2d1190(0x2b6e5d2d03c0) chain { }
adding 4:  27 (expr_list:REG_DEAD (reg/v:SI 32 [ y ])
    (nil))
  regular looking at use u-1 reg 35 bb 3 insn 27 flag 0x0 type 0x1 loc 0x2b6e5d2d1188(0x2b6e5d2d0420) chain { }
adding 4:  27 (expr_list:REG_DEAD (reg:SI 35 [ D.1588 ])
    (expr_list:REG_DEAD (reg/v:SI 32 [ y ])
        (nil)))
deleting:  25 (expr_list:REG_DEAD (reg:SI 8 %a0)
    (nil))
  regular looking at use u-1 reg 8 bb 3 insn 25 flag 0x800 type 0x1 loc 0x2b6e5d2d1150(0x2b6e5d2d0d60) chain { }
adding 4:  25 (expr_list:REG_DEAD (reg:SI 8 %a0)
    (nil))
  regular looking at use u-1 reg 24 bb 3 insn 25 flag 0x0 type 0x3 loc 0x2b6e5d2d1c48(0x2b6e5c985040) chain { }
  regular looking at def d34 reg 15 bb 3 insn 24 flag 0x800 type 0x0 loc 0x2b6e5d2d0f88(0x2b6e5c985000) chain { }
  regular looking at use u21 reg 15 bb 3 insn 24 flag 0x800 type 0x1 loc 0x2b6e5d2d0f68(0x2b6e5c985000) chain { }
processing call 22
  live = 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr] 32 35
  regular looking at def d-1 reg 8 bb 3 insn 22 flag 0x800 type 0x0 loc 0x2b6e5d2d0ec8(0x2b6e5d2d0d60) chain { }
  regular looking at use u-1 reg 15 bb 3 insn 22 flag 0xa00 type 0x1 chain { }
  regular looking at def d35 reg 15 bb 3 insn 20 flag 0x901 type 0x0 loc 0x2b6e5c9aaf28(0x2b6e5c985000) chain { }
  regular looking at use u17 reg 15 bb 3 insn 20 flag 0x800 type 0x3 loc 0x2b6e5c9aaf28(0x2b6e5c985000) chain { }
  regular looking at def d36 reg 15 bb 3 insn 19 flag 0x901 type 0x0 loc 0x2b6e5c9aaf18(0x2b6e5c985000) chain { }
  regular looking at use u16 reg 15 bb 3 insn 19 flag 0x800 type 0x3 loc 0x2b6e5c9aaf18(0x2b6e5c985000) chain { }
  regular looking at def d59 reg 35 bb 3 insn 18 flag 0x0 type 0x0 loc 0x2b6e5d2d0c68(0x2b6e5d2d0420) chain { }
  regular looking at use u15 reg 0 bb 3 insn 18 flag 0x800 type 0x1 loc 0x2b6e5d2d0c70(0x2b6e5d2d0b60) chain { }
processing call 17
  live = 0 [%d0] 14 [%a6] 15 [%sp] 24 [%argptr] 32
  regular looking at def d-1 reg 0 bb 3 insn 17 flag 0x800 type 0x0 loc 0x2b6e5d2d0c48(0x2b6e5d2d0b60) chain { }
  regular looking at use u-1 reg 15 bb 3 insn 17 flag 0xa00 type 0x1 chain { }
  regular looking at def d37 reg 15 bb 3 insn 15 flag 0x901 type 0x0 loc 0x2b6e5c9aaef8(0x2b6e5c985000) chain { }
  regular looking at use u12 reg 15 bb 3 insn 15 flag 0x800 type 0x3 loc 0x2b6e5c9aaef8(0x2b6e5c985000) chain { }
deleting:  14 (expr_list:REG_DEAD (reg:SI 0 %d0)
    (nil))
  regular looking at def d57 reg 32 bb 3 insn 14 flag 0x0 type 0x0 loc 0x2b6e5d2d0aa8(0x2b6e5d2d03c0) chain { }
  regular looking at use u11 reg 0 bb 3 insn 14 flag 0x800 type 0x1 loc 0x2b6e5d2d0ab0(0x2b6e5d2d0980) chain { }
adding 4:  14 (expr_list:REG_DEAD (reg:SI 0 %d0)
    (nil))
processing call 13
  live = 0 [%d0] 14 [%a6] 15 [%sp] 24 [%argptr]
  regular looking at def d-1 reg 0 bb 3 insn 13 flag 0x800 type 0x0 loc 0x2b6e5d2d0a88(0x2b6e5d2d0980) chain { }
  regular looking at use u-1 reg 15 bb 3 insn 13 flag 0xa00 type 0x1 chain { }
  regular looking at def d38 reg 15 bb 3 insn 11 flag 0x901 type 0x0 loc 0x2b6e5c9aaee8(0x2b6e5c985000) chain { }
  regular looking at use u8 reg 15 bb 3 insn 11 flag 0x800 type 0x3 loc 0x2b6e5c9aaee8(0x2b6e5c985000) chain { }
live at bottom  0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]
live before artificials out  0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]
processing call 46
  live = 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]
  regular looking at def d14 reg 8 bb 4 insn 46 flag 0x800 type 0x0 loc 0x2b6e5d2d1948(0x2b6e5d2d17a0) chain { }
  regular looking at use u47 reg 15 bb 4 insn 46 flag 0xa00 type 0x1 chain { }
deleting:  45 (expr_list:REG_DEAD (reg/v:SI 30 [ z ])
    (nil))
  regular looking at use u-1 reg 0 bb 4 insn 45 flag 0x800 type 0x1 loc 0x2b6e5d2d1888(0x2b6e5d2d14a0) chain { }
  regular looking at use u-1 reg 24 bb 4 insn 45 flag 0x0 type 0x3 loc 0x2b6e5d2d1d28(0x2b6e5c985040) chain { }
  regular looking at use u-1 reg 30 bb 4 insn 45 flag 0x0 type 0x1 loc 0x2b6e5d2d1890(0x2b6e5d2d0380) chain { }
adding 4:  45 (expr_list:REG_DEAD (reg/v:SI 30 [ z ])
    (nil))
  regular looking at use u42 reg 24 bb 4 insn 43 flag 0x0 type 0x3 loc 0x2b6e5d2d1ce8(0x2b6e5c985040) chain { }
  regular looking at def d31 reg 15 bb 4 insn 42 flag 0x800 type 0x0 loc 0x2b6e5d2d1648(0x2b6e5c985000) chain { }
  regular looking at use u41 reg 15 bb 4 insn 42 flag 0x800 type 0x1 loc 0x2b6e5d2d1628(0x2b6e5c985000) chain { }
processing call 40
  live = 0 [%d0] 14 [%a6] 15 [%sp] 24 [%argptr] 30
  regular looking at def d-1 reg 0 bb 4 insn 40 flag 0x800 type 0x0 loc 0x2b6e5d2d1588(0x2b6e5d2d14a0) chain { }
  regular looking at use u-1 reg 15 bb 4 insn 40 flag 0xa00 type 0x1 chain { }
  regular looking at def d32 reg 15 bb 4 insn 38 flag 0x901 type 0x0 loc 0x2b6e5c9aaf58(0x2b6e5c985000) chain { }
  regular looking at use u36 reg 15 bb 4 insn 38 flag 0x800 type 0x3 loc 0x2b6e5c9aaf58(0x2b6e5c985000) chain { }
  regular looking at use u37 reg 30 bb 4 insn 38 flag 0x0 type 0x1 loc 0x2b6e5d2d14f0(0x2b6e5d2d0380) chain { }
deleting:  37 (expr_list:REG_DEAD (reg:SI 0 %d0)
    (nil))
  regular looking at def d55 reg 30 bb 4 insn 37 flag 0x0 type 0x0 loc 0x2b6e5d2d1428(0x2b6e5d2d0380) chain { }
  regular looking at use u35 reg 0 bb 4 insn 37 flag 0x800 type 0x1 loc 0x2b6e5d2d1430(0x2b6e5d2d1320) chain { }
adding 4:  37 (expr_list:REG_DEAD (reg:SI 0 %d0)
    (nil))
processing call 36
  live = 0 [%d0] 14 [%a6] 15 [%sp] 24 [%argptr]
  regular looking at def d-1 reg 0 bb 4 insn 36 flag 0x800 type 0x0 loc 0x2b6e5d2d1408(0x2b6e5d2d1320) chain { }
  regular looking at use u-1 reg 15 bb 4 insn 36 flag 0xa00 type 0x1 chain { }
  regular looking at def d33 reg 15 bb 4 insn 34 flag 0x901 type 0x0 loc 0x2b6e5c9aaf48(0x2b6e5c985000) chain { }
  regular looking at use u32 reg 15 bb 4 insn 34 flag 0x800 type 0x3 loc 0x2b6e5c9aaf48(0x2b6e5c985000) chain { }


Pass 0

  Register 30 costs: DATA_REGS:3240 ADDR_REGS:3240 GENERAL_REGS:3240 DATA_OR_FP_REGS:6480 ADDR_OR_FP_REGS:6480 ALL_REGS:6480 MEM:8100
  Register 32 costs: DATA_REGS:2760 ADDR_REGS:2760 GENERAL_REGS:2760 DATA_OR_FP_REGS:4600 ADDR_OR_FP_REGS:4600 ALL_REGS:4600 MEM:5980
  Register 35 costs: DATA_REGS:2760 ADDR_REGS:2760 GENERAL_REGS:2760 DATA_OR_FP_REGS:4600 ADDR_OR_FP_REGS:4600 ALL_REGS:4600 MEM:5980

  Register 30 pref GENERAL_REGS
  Register 32 pref GENERAL_REGS
  Register 35 pref GENERAL_REGS


Pass 1

  Register 30 costs: DATA_REGS:3240 ADDR_REGS:3240 GENERAL_REGS:3240 DATA_OR_FP_REGS:6480 ADDR_OR_FP_REGS:6480 ALL_REGS:6480 MEM:8100
  Register 32 costs: DATA_REGS:3680 ADDR_REGS:3680 GENERAL_REGS:3680 DATA_OR_FP_REGS:5520 ADDR_OR_FP_REGS:5520 ALL_REGS:5520 MEM:6900
  Register 35 costs: DATA_REGS:3680 ADDR_REGS:3680 GENERAL_REGS:3680 DATA_OR_FP_REGS:5520 ADDR_OR_FP_REGS:5520 ALL_REGS:5520 MEM:6900

51 registers.

Register 25 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.

Register 26 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.

Register 27 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.

Register 28 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.

Register 29 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.

Register 30 used 3 times across 6 insns in block 4; set 1 time; user var; crosses 1 call.

Register 31 used 0 times across 0 insns; set 0 times; user var; dies in 0 places; NO_REGS or none; pointer.

Register 32 used 2 times across 10 insns in block 3; set 1 time; user var; crosses 2 calls.

Register 33 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 34 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 35 used 2 times across 7 insns in block 3; set 1 time; crosses 1 call.

Register 36 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 37 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 38 used 0 times across 0 insns; set 0 times; user var; dies in 0 places; NO_REGS or none.

Register 39 used 0 times across 0 insns; set 0 times; user var; dies in 0 places; NO_REGS or none.

Register 40 used 0 times across 0 insns; set 0 times; user var; dies in 0 places; NO_REGS or none.

Register 41 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.

Register 42 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.

Register 43 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.

Register 44 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 45 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.

Register 46 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.

Register 47 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 48 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 49 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

Register 50 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.

5 basic blocks, 5 edges.

Basic block 2 , prev 0, next 3, loop_depth 0, count 0, freq 10000, maybe hot.
Predecessors:  ENTRY [100.0%]  (fallthru)
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(14){ }u1(15){ }u2(24){ }}
;; lr  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  use 	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  def 	
;; urec  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  gen 	
;; urec  kill	
;; urec  ec	

Successors:  3 [46.0%]  (fallthru) 4 [54.0%] 
;; lr  out 	 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  out 	 14 [%a6] 15 [%sp] 24 [%argptr]


Basic block 3 , prev 2, next 4, loop_depth 0, count 0, freq 4600, maybe hot.
Predecessors:  2 [46.0%]  (fallthru)
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u5(14){ }u6(15){ }u7(24){ }}
;; lr  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  use 	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  def 	 0 [%d0] 1 [%d1] 8 [%a0] 9 [%a1] 15 [%sp] 16 [%fp0] 17 [%fp1] 32 35
;; urec  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  gen 	 0 [%d0] 8 [%a0] 15 [%sp] 32 35
;; urec  kill	 0 [%d0] 8 [%a0] 15 [%sp] 32 35
;; urec  ec	

Successors:  EXIT [100.0%]  (ab,sibcall)
;; lr  out 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  out 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]


Basic block 4 , prev 3, next 1, loop_depth 0, count 0, freq 5400, maybe hot.
Predecessors:  2 [54.0%] 
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u29(14){ }u30(15){ }u31(24){ }}
;; lr  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  use 	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  def 	 0 [%d0] 1 [%d1] 8 [%a0] 9 [%a1] 15 [%sp] 16 [%fp0] 17 [%fp1] 30
;; urec  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  gen 	 0 [%d0] 8 [%a0] 15 [%sp] 30
;; urec  kill	 0 [%d0] 8 [%a0] 15 [%sp] 30
;; urec  ec	

Successors:  EXIT [100.0%]  (ab,sibcall)
;; lr  out 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  out 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]


;; Register 30 in 2.
;; Register 32 in 3.
;; Register 35 in 2.


f

Dataflow summary:
;;  invalidated by call 	 0 [%d0] 1 [%d1] 8 [%a0] 9 [%a1] 16 [%fp0] 17 [%fp1]
;;  hardware regs used 	 14 [%a6] 15 [%sp] 24 [%argptr]
;;  regular block artificial uses 	 14 [%a6] 15 [%sp] 24 [%argptr]
;;  eh block artificial uses 	 14 [%a6] 15 [%sp] 24 [%argptr]
;;  entry block defs 	 8 [%a0] 9 [%a1] 14 [%a6] 15 [%sp] 24 [%argptr]
;;  exit block uses 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp]
;;  regs ever live 	 0[%d0] 8[%a0] 15[%sp]
(note 1 0 6)

;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(14){ }u1(15){ }u2(24){ }}
;; lr  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  use 	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  def 	
;; urec  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  gen 	
;; urec  kill	
;; urec  ec	

;; Pred edge  ENTRY [100.0%]  (fallthru)
(note 6 1 2 2 [bb 2])

(note 2 6 5 2)

(note 5 2 8 2)

(insn:QI 8 5 9 2 test.c:8 (set (cc0)
        (mem/c/i:SI (plus:SI (reg/f:SI 24 %argptr)
                (const_int 8 [0x8])) [3 x+0 S4 A32])) 3 {*m68k.md:221} (nil))

(jump_insn 9 8 10 2 test.c:8 (set (pc)
        (if_then_else (eq (cc0)
                (const_int 0 [0x0]))
            (label_ref 32)
            (pc))) 386 {beq} (expr_list:REG_BR_PROB (const_int 5400 [0x1518])
        (nil)))
;; End of basic block 2 -> ( 3 4)
;; lr  out 	 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  out 	 14 [%a6] 15 [%sp] 24 [%argptr]


;; Succ edge  3 [46.0%]  (fallthru)
;; Succ edge  4 [54.0%] 

;; Start of basic block ( 2) -> 3
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u5(14){ }u6(15){ }u7(24){ }}
;; lr  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  use 	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  def 	 0 [%d0] 1 [%d1] 8 [%a0] 9 [%a1] 15 [%sp] 16 [%fp0] 17 [%fp1] 32 35
;; urec  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  gen 	 0 [%d0] 8 [%a0] 15 [%sp] 32 35
;; urec  kill	 0 [%d0] 8 [%a0] 15 [%sp] 32 35
;; urec  ec	

;; Pred edge  2 [46.0%]  (fallthru)
(note 10 9 11 3 [bb 3])

(insn 11 10 12 3 test.c:9 (set (mem/i:SI (pre_dec:SI (reg/f:SI 15 %sp)) [0 S4 A16])
        (const_int 1 [0x1])) 29 {pushexthisi_const} (nil))

(note 12 11 13 3)

(call_insn 13 12 14 3 test.c:9 (set (reg:SI 0 %d0)
        (call (mem:QI (symbol_ref:SI ("fi1") [flags 0x41] <function_decl 0x2b6e5d2b4700 fi1>) [0 S1 A8])
            (const_int 4 [0x4]))) 432 {*call_value} (nil)
    (nil))

(insn 14 13 15 3 test.c:9 (set (reg/v:SI 32 [ y ])
        (reg:SI 0 %d0)) 31 {*m68k.md:679} (expr_list:REG_DEAD (reg:SI 0 %d0)
        (nil)))

(insn 15 14 16 3 test.c:11 (set (mem/i:SI (pre_dec:SI (reg/f:SI 15 %sp)) [0 S4 A16])
        (const_int 3 [0x3])) 29 {pushexthisi_const} (nil))

(note 16 15 17 3)

(call_insn 17 16 18 3 test.c:11 (set (reg:SI 0 %d0)
        (call (mem:QI (symbol_ref:SI ("fi2") [flags 0x41] <function_decl 0x2b6e5d2b4800 fi2>) [0 S1 A8])
            (const_int 4 [0x4]))) 432 {*call_value} (nil)
    (nil))

(insn 18 17 19 3 test.c:11 (set (reg:SI 35 [ D.1588 ])
        (reg:SI 0 %d0)) 31 {*m68k.md:679} (nil))

(insn 19 18 20 3 test.c:12 (set (mem/f/i:SI (pre_dec:SI (reg/f:SI 15 %sp)) [0 S4 A16])
        (const_int 0 [0x0])) 29 {pushexthisi_const} (nil))

(insn 20 19 21 3 test.c:12 (set (mem/i:SI (pre_dec:SI (reg/f:SI 15 %sp)) [0 S4 A16])
        (const_int 2 [0x2])) 29 {pushexthisi_const} (nil))

(note 21 20 22 3)

(call_insn 22 21 23 3 test.c:12 (set (reg:SI 8 %a0)
        (call (mem:QI (symbol_ref:SI ("fp1") [flags 0x41] <function_decl 0x2b6e5d2b4900 fp1>) [0 S1 A8])
            (const_int 8 [0x8]))) 432 {*call_value} (nil)
    (nil))

(note 23 22 24 3)

(insn 24 23 25 3 test.c:13 (set (reg/f:SI 15 %sp)
        (plus:SI (reg/f:SI 15 %sp)
            (const_int 16 [0x10]))) 127 {*addsi3_internal} (nil))

(insn 25 24 26 3 test.c:13 (set (mem:SI (plus:SI (reg/f:SI 24 %argptr)
                (const_int 12 [0xc])) [0 S4 A32])
        (reg:SI 8 %a0)) 31 {*m68k.md:679} (expr_list:REG_DEAD (reg:SI 8 %a0)
        (nil)))

(note 26 25 27 3)

(insn 27 26 28 3 test.c:13 (set (mem:SI (plus:SI (reg/f:SI 24 %argptr)
                (const_int 8 [0x8])) [0 S4 A32])
        (plus:SI (reg:SI 35 [ D.1588 ])
            (reg/v:SI 32 [ y ]))) 127 {*addsi3_internal} (expr_list:REG_DEAD (reg:SI 35 [ D.1588 ])
        (expr_list:REG_DEAD (reg/v:SI 32 [ y ])
            (nil))))

(call_insn/j 28 27 29 3 test.c:13 (set (reg:SI 8 %a0)
        (call (mem:QI (symbol_ref:SI ("fp1") [flags 0x41] <function_decl 0x2b6e5d2b4900 fp1>) [0 S1 A8])
            (const_int 8 [0x8]))) 430 {*sibcall_value} (nil)
    (nil))
;; End of basic block 3 -> ( 1)
;; lr  out 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  out 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]


;; Succ edge  EXIT [100.0%]  (ab,sibcall)

(barrier 29 28 32)

;; Start of basic block ( 2) -> 4
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u29(14){ }u30(15){ }u31(24){ }}
;; lr  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  use 	 14 [%a6] 15 [%sp] 24 [%argptr]
;; lr  def 	 0 [%d0] 1 [%d1] 8 [%a0] 9 [%a1] 15 [%sp] 16 [%fp0] 17 [%fp1] 30
;; urec  in  	 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  gen 	 0 [%d0] 8 [%a0] 15 [%sp] 30
;; urec  kill	 0 [%d0] 8 [%a0] 15 [%sp] 30
;; urec  ec	

;; Pred edge  2 [54.0%] 
(code_label 32 29 33 4 2 "" [1 uses])

(note 33 32 34 4 [bb 4])

(insn 34 33 35 4 test.c:15 (set (mem/i:SI (pre_dec:SI (reg/f:SI 15 %sp)) [0 S4 A16])
        (const_int 2 [0x2])) 29 {pushexthisi_const} (nil))

(note 35 34 36 4)

(call_insn 36 35 37 4 test.c:15 (set (reg:SI 0 %d0)
        (call (mem:QI (symbol_ref:SI ("fi2") [flags 0x41] <function_decl 0x2b6e5d2b4800 fi2>) [0 S1 A8])
            (const_int 4 [0x4]))) 432 {*call_value} (nil)
    (nil))

(insn 37 36 38 4 test.c:15 (set (reg/v:SI 30 [ z ])
        (reg:SI 0 %d0)) 31 {*m68k.md:679} (expr_list:REG_DEAD (reg:SI 0 %d0)
        (nil)))

(insn 38 37 39 4 test.c:16 (set (mem/i:SI (pre_dec:SI (reg/f:SI 15 %sp)) [0 S4 A16])
        (reg/v:SI 30 [ z ])) 31 {*m68k.md:679} (nil))

(note 39 38 40 4)

(call_insn 40 39 41 4 test.c:16 (set (reg:SI 0 %d0)
        (call (mem:QI (symbol_ref:SI ("fi1") [flags 0x41] <function_decl 0x2b6e5d2b4700 fi1>) [0 S1 A8])
            (const_int 4 [0x4]))) 432 {*call_value} (nil)
    (nil))

(note 41 40 42 4)

(insn 42 41 43 4 test.c:17 (set (reg/f:SI 15 %sp)
        (plus:SI (reg/f:SI 15 %sp)
            (const_int 8 [0x8]))) 127 {*addsi3_internal} (nil))

(insn 43 42 44 4 test.c:17 (set (mem:SI (plus:SI (reg/f:SI 24 %argptr)
                (const_int 12 [0xc])) [0 S4 A32])
        (const_int 3 [0x3])) 31 {*m68k.md:679} (nil))

(note 44 43 45 4)

(insn 45 44 46 4 test.c:17 (set (mem:SI (plus:SI (reg/f:SI 24 %argptr)
                (const_int 8 [0x8])) [0 S4 A32])
        (plus:SI (reg:SI 0 %d0)
            (reg/v:SI 30 [ z ]))) 127 {*addsi3_internal} (expr_list:REG_DEAD (reg/v:SI 30 [ z ])
        (nil)))

(call_insn/j 46 45 47 4 test.c:17 (set (reg:SI 8 %a0)
        (call (mem:QI (symbol_ref:SI ("fp2") [flags 0x41] <function_decl 0x2b6e5d2b4a00 fp2>) [0 S1 A8])
            (const_int 8 [0x8]))) 430 {*sibcall_value} (nil)
    (nil))
;; End of basic block 4 -> ( 1)
;; lr  out 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]
;; urec  out 	 0 [%d0] 8 [%a0] 14 [%a6] 15 [%sp] 24 [%argptr]


;; Succ edge  EXIT [100.0%]  (ab,sibcall)

(barrier 47 46 0)


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