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Re: Improvements of the haifa scheduler

From: "Vladimir N. Makarov" <vmakarov at redhat dot com>
To: Andrew Pinski <pinskia at gmail dot com>
Cc: Maxim Kuvyrkov <mkuvyrkov at ispras dot ru>, Jim Wilson <wilson at specifix dot com>, Ayal Zaks <ZAKS at il dot ibm dot com>, Andrey Belevantsev <abel at ispras dot ru>, gcc at gcc dot gnu dot org, Ian Lance Taylor <iant at google dot com>
Date: Sun, 04 Mar 2007 14:36:01 -0500
Subject: Re: Improvements of the haifa scheduler
References: <45EA972B.9080902@ispras.ru> <45EAD89A.5010907@redhat.com> <de8d50360703040934n57de2721k63ccbc54a0551e81@mail.gmail.com>

Andrew Pinski wrote:

On 3/4/07, Vladimir N. Makarov <vmakarov@redhat.com> wrote:

Another important thing to do is to make the 1st scheduler register
pressure sensitive.

I don't know how many times this has to be said, no this is not the
correct approach to fix that issue.  The correct fix is able for the
register allocator to work correctly and fix up the IR.

I am not agree. Fixing it in RA after insn with hard register moved will result in several additional insns of course unless you implement moving insns in RA which makes it an insn scheduler. Also fixing this in the reload is much more difficult task (needs more expertise) than in the insn scheduler. Ideally integrated RA and scheduler (and code selection) would be best solution but it is not realistic becuase even after many years gcc has no decent separate scheduler and RA.

References:
- Improvements of the haifa scheduler
  - From: Maxim Kuvyrkov
- Re: Improvements of the haifa scheduler
  - From: Vladimir N. Makarov
- Re: Improvements of the haifa scheduler
  - From: Andrew Pinski

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