trying to fix a bug in m6812 front-end

[Sean D'Epagnier <sean at depagnier dot com>]

I am using gcc 3.3.5 with the latest m68hc1x patches to compile programs for a
9s12 processor, and cc1 calls abort when compiling the following code:

void func()
{
  short a, *b;
  a &= *b;
}

The rtl for the instructions dump as follows:

-> (insn 9 6 10 (nil) (set (reg:HI 53)
->         (mem/f:HI (reg/f:HI 49 virtual-stack-vars) [0 a+0 S2 A16])) -1 (nil)
->     (nil))
-> 
-> (insn 10 9 11 (nil) (set (reg:HI 54)
->         (and:HI (reg:HI 53)
->             (mem:HI (mem/f:HI (plus:HI (reg/f:HI 49 virtual-stack-vars)
->                         (const_int 2 [0x2])) [0 b+0 S2 A16]) [0 S2 A8]))) -1 (nil)
->     (nil))
-> 
-> (insn 11 10 12 (nil) (set (mem/f:HI (reg/f:HI 49 virtual-stack-vars) [0 a+0 S2 A16])
->         (reg:HI 54)) -1 (nil)
->     (nil))


If I modify the '&=' to '|=' instead, the code compiles fine with the following rtl:

-> (insn 9 6 10 (nil) (set (reg:HI 53)
->         (mem/f:HI (reg/f:HI 49 virtual-stack-vars) [0 a+0 S2 A16])) -1 (nil)
->     (nil))
-> 
-> (insn 10 9 11 (nil) (set (reg:HI 54)
->         (mem:HI (mem/f:HI (plus:HI (reg/f:HI 49 virtual-stack-vars)
->                     (const_int 2 [0x2])) [0 b+0 S2 A16]) [0 S2 A8])) -1 (nil)
->     (nil))
-> 
-> (insn 11 10 12 (nil) (set (reg:HI 55)
->         (ior:HI (reg:HI 53)
->             (reg:HI 54))) -1 (nil)
->     (nil))
-> 
-> (insn 12 11 13 (nil) (set (mem/f:HI (reg/f:HI 49 virtual-stack-vars) [0 a+0 S2 A16])
->         (reg:HI 55)) -1 (nil)
->     (nil))
 

It looks like somewhere before generating rtl in the second case, it split the instruction
as this architecture cannot handle the second instruction in the first case. xor behaves
similarly to or and works as well.

I am trying to find out what part of gcc to look in so I can make the change so that the and
instruction is handled the same way.

Any hints are much appreciated.

--
Sean D'Epagnier