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reduction of GP registers in MIPS backend


In http://gcc.gnu.org/ml/gcc/2006-07/msg00632.html, you wrote:

dp-bit.c: In function '__muldf3':
dp-bit.c:953: error: insn does not satisfy its constraints:
(insn 677 231 616 19 dp-bit.c:871 (set (reg/v:DI 24 $24 [orig:55 res2 ] [55])
      (reg:DI 2 $2)) 3 {*movdi_32bit} (nil)
  (nil))
dp-bit.c:953: internal compiler error: in
reload_cse_simplify_operands, at postreload.c:394

please read the documentation in gcc/gcc/doc/ ; this is explained in tm.texi,
under HARD_REGNO_MODE_OK.

{ 0x01ffffff, 0x00000000, }, /* integer registers */ \

This violates an assumption in mips.c:override_options that GPRs come in pairs. Thus you end up with (reg/v:DI 24 $24 [orig:55 res2 ] [55]), which does not satisfy the 'd' constraint.


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