Re: Modifying ARM code generator for elimination of 8bit writes - need help

[Rask Ingemann Lambertsen <rask at sygehus dot dk>]

On Wed, Jun 07, 2006 at 07:22:31AM +0200, Wolfgang Mües wrote:
> On Tuesday 06 June 2006 21:33, Rask Ingemann Lambertsen wrote:
> 
> > Yet another register which stands a good chance of being reusable is
> > the register containing the address.
> 
> Yes, but that is not allowed according to the specification of the swp 
> instruction. The address register must be different from the other 2 
> registers. Is there any chance of gcc violating this constraint? 

Yes. :-(

$ awk 'BEGIN { FS="[][\t ,]"; } $2 ~ /^swp/ && ($3 == $5 || $3 == $8 || \
$5 == $8) { print; }' fs/vfat/namei.s
        swpb    r6, r3, [r6]

The only fix I can think of is to mark the scratch register as
early-clobbered, but we preferably don't want to do that, because then it
can't be identical to the input register. Actually, this may work, but I
can't test it right now because the previous recompile hasn't finished yet:

;; This is primarily a hack for the Nintendo DS external RAM.
(define_insn "_arm_movqi_insn_swp"
  [(set (match_operand:QI 0 "reg_or_Qmem_operand" "=r,r,r,Q,Q")
	(match_operand:QI 1 "general_operand" "rI,K,m,r,r"))
        (clobber (match_scratch:QI 2 "=X,X,X,1,&r"))]
  "TARGET_ARM && TARGET_SWP_BYTE_WRITES
   && (   register_operand (operands[0], QImode)
       || register_operand (operands[1], QImode))"
  "@
   mov%?\\t%0, %1
   mvn%?\\t%0, #%B1
   ldr%?b\\t%0, %1
   swp%?b\\t%1, %1, [%|%m0]
   swp%?b\\t%2, %1, [%|%m0]"
  [(set_attr "type" "*,*,load1,store1,store1")
   (set_attr "predicable" "yes")]
)

-- 
Rask Ingemann Lambertsen