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Re: Modifying ARM code generator for elimination of 8bit writes - need help


Hello,

my first little success...

in arm.h, I have changed

> /* Output the address of an operand.  */
> #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X)			\
> {									\
>     int is_minus = GET_CODE (X) == MINUS;					\
> 									\
>     if (GET_CODE (X) == REG)						\
>       asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); 				\

into

> /* Output the address of an operand.  */
> #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X)			\
> {									\
>     int is_minus = GET_CODE (X) == MINUS;					\
> 									\
>     if (GET_CODE (X) == REG)						\
>       asm_fprintf (STREAM, "[%r]", REGNO (X));				\

I don't know why the form "[%r, #0]" was coded before, because the 
assembler understands "[%r]" very well for all instructions. The form 
"[%r]" has a wider usage because it covers swp too.

On Sunday 04 June 2006 23:36, Rask Ingemann Lambertsen wrote:
> On Wed, May 31, 2006 at 10:49:35PM +0200, Wolfgang Mües wrote:
> > > (define_insn "*arm_movqi_insn"
> > >   [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
> > > 	(match_operand:QI 1 "general_operand" "rI,K,m,r"))]

> I think you should go back to this (i.e. the unmodified version) and
> only change the "m" into "Q" in the fourth alternative of operand 0.
> See if that works, i.e. generates addresses that are valid for the
> swp instruction.

No, that doesn't work:

> ../../../gcc-4.0.2/gcc/unwind-dw2-fde.c: In function
> __register_frame_info_table_bases':
> ../../../gcc-4.0.2/gcc/unwind-dw2-fde.c:146: error: insn does not
> satisfy its constraints: (insn 63 28 29 0
> ../../../gcc-4.0.2/gcc/unwind-dw2-fde.c:136 (set (mem/s/j:QI (plus:SI
> (reg/v/f:SI 1 r1 [orig:102 ob ] [102]) (const_int 16 [0x10])) [0 S1
> A32])
>         (reg:QI 12 ip)) 155 {*arm_movqi_insn} (nil)
>     (nil))
> ../../../gcc-4.0.2/gcc/unwind-dw2-fde.c:146: internal compiler error:
> in reload_ cse_simplify_operands, at postreload.c:391

Also, I wonder what the "Q" constraint really means:

from the GCC manual:

> Q
> A memory reference where the exact address is in a single register
> (``m'' is preferable for asm statements)

but in arm.h:

> /* For the ARM, `Q' means that this is a memory operand that is just
>    an offset from a register.
> #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR)			\
>    ((C) == 'Q') ? (GET_CODE (OP) == MEM					\
> 		 && GET_CODE (XEXP (OP, 0)) == REG) :			\

Obviously, GCC tries to implement REG+CONSTANT with Q.

Maybe I must define a new constraint?

regards

Wolfgang
-- 
We're back to the times when men were men 
and wrote their own device drivers.

(Linus Torvalds)


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