This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: Modifying ARM code generator for elimination of 8bit writes - need help
- From: Rask Ingemann Lambertsen <rask at sygehus dot dk>
- To: Wolfgang Mües <wolfgang at iksw-muees dot de>
- Cc: gcc at gcc dot gnu dot org
- Date: Sun, 4 Jun 2006 23:36:37 +0200
- Subject: Re: Modifying ARM code generator for elimination of 8bit writes - need help
- References: <200605282223.33002.wolfgang@iksw-muees.de> <200605302103.55354.paul@codesourcery.com> <200605312249.35517.wolfgang@iksw-muees.de>
On Wed, May 31, 2006 at 10:49:35PM +0200, Wolfgang Mües wrote:
> > (define_insn "*arm_movqi_insn"
> > [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
> > (match_operand:QI 1 "general_operand" "rI,K,m,r"))]
> > "TARGET_ARM
> > && ( register_operand (operands[0], QImode)
> >
> > || register_operand (operands[1], QImode))"
> >
> > "@
> > mov%?\\t%0, %1
> > mvn%?\\t%0, #%B1
> > ldr%?b\\t%0, %1
> > str%?b\\t%1, %0"
> > [(set_attr "type" "*,*,load1,store1")
> > (set_attr "predicable" "yes")]
> > )
I think you should go back to this (i.e. the unmodified version) and only
change the "m" into "Q" in the fourth alternative of operand 0. See if that
works, i.e. generates addresses that are valid for the swp instruction. If
it does, then begin to add other changes.
--
Rask Ingemann Lambertsen