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Re: Modifying ARM code generator for elimination of 8bit writes - need help
- From: Rask Ingemann Lambertsen <rask at sygehus dot dk>
- To: Wolfgang Mües <wolfgang at iksw-muees dot de>
- Cc: gcc at gcc dot gnu dot org
- Date: Thu, 1 Jun 2006 16:13:46 +0200
- Subject: Re: Modifying ARM code generator for elimination of 8bit writes - need help
- References: <200605282223.33002.wolfgang@iksw-muees.de> <200605302103.55354.paul@codesourcery.com> <200605312249.35517.wolfgang@iksw-muees.de>
On Wed, May 31, 2006 at 10:49:35PM +0200, Wolfgang Mües wrote:
> > (define_insn "*arm_movqi_insn"
> > [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,Q")
> > (match_operand:QI 1 "general_operand" "rI,K,m,+r"))]
> > "TARGET_ARM
> > && ( register_operand (operands[0], QImode)
> >
> > || register_operand (operands[1], QImode))"
> >
> > "@
> > mov%?\\t%0, %1
> > mvn%?\\t%0, #%B1
> > ldr%?b\\t%0, %1
> > swp%?b\\t%1, %1, [%M0]"
> > [(set_attr "type" "*,*,load1,store1")
> > (set_attr "predicable" "yes")]
> > )
>
> Changing "m" to "Q", narrowing the address modes
> Changing "r" to "+r", (register is globbered)
> and of course making the swpb call..
I think you will need to remove the '+' as already suggested and add
(clobber (match_scratch:QI "=X,X,X,1")) to tell GCC that the register
allocated to operand 1 is clobbered by the instruction for this particular
alternative. You will also have to modify any code which expands this
pattern accordingly.
--
Rask Ingemann Lambertsen