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Re: Questions about comparison insns in mips.md

From: Ian Lance Taylor <ian at airs dot com>
To: Eric Fisher <joefoxreal at gmail dot com>
Cc: gcc at gcc dot gnu dot org
Date: 08 Oct 2005 21:57:45 -0700
Subject: Re: Questions about comparison insns in mips.md
References: <d6afecde0510080006j526f418ew@mail.gmail.com><m3ek6v29gn.fsf@gossamer.airs.com><d6afecde0510081840q7fb83421l@mail.gmail.com>

Eric Fisher <joefoxreal@gmail.com> writes:

> Thanks for the help. Since ARM has condition codes, I'm wondering why it uses
> a psuedo register internally to represent things that use or set the
> condition codes?
> I think it should use CPSR directly.

ARM actually does use the CPSR directly.  See CC_REGNUM.  The
comparison instructions are not generated directly because ARM uses
different comparison modes depending upon how the comparison is being
used, and it uses those modes for optimizations.  See
arm_select_cc_mode in arm.c.  See uses of CC_NOOV in arm.md.

Ian

References:
- Questions about comparison insns in mips.md
  - From: Eric Fisher
- Re: Questions about comparison insns in mips.md
  - From: Ian Lance Taylor
- Re: Questions about comparison insns in mips.md
  - From: Eric Fisher

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