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Re: OT: How is memory latency important on AMD64 box while compilinglarge C/C++ sources
- From: Karel Gardas <kgardas at objectsecurity dot com>
- To: GCC Mailing List <gcc at gcc dot gnu dot org>
- Date: Tue, 12 Apr 2005 15:38:23 +0200 (CEST)
- Subject: Re: OT: How is memory latency important on AMD64 box while compilinglarge C/C++ sources
On Tue, 12 Apr 2005, Karel Gardas wrote:
> using cache and how much cache it needs (I'm cosidering 512KB cache CPU
> here either Winchester or Venice core) and that's the reason why I ask
> here, since I've not been able so far to search by google for sufficient
> answer for this question.
Also the reason why I'm asking here about this, is this Mike Stump's post:
Especially: ``Currently gcc takes a cache miss every 20 instructions, or
some ungodly number, and that really saps performance.''
but I don't know if this is just an 1st April fool joke or the reality and
if I understand "cache miss" right and if this is L1 or L2 cache miss.
Karel Gardas firstname.lastname@example.org
ObjectSecurity Ltd. http://www.objectsecurity.com