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Re: PR target/17101: question about powerpc s<cond> expanders
On Fri, Nov 12, 2004 at 06:37:39PM +0000, Nathan Sidwell wrote:
> David Edelsohn wrote:
>
> >Nathan> why is that? The unsigned variants are not so encumbered.
> >
> > There are short, straight-line PowerPC code sequences for
> >unsigned, but not for signed. The signed sequences use the POWER "doz"
> >instruction that was removed from PowerPC.
>
> that is not what I observe, when I remove the TARGET_POWER check.
> For instance, V > 55
> .sgt:
> cmpwi 7,3,55
> mfcr 3
> rlwinm 3,3,30,1
> is that worse than
> li 9,0
> cmpwe 7,3,55
> ble- 7,.skip
> li 9,1
> .skip:
Wouldn't the best solution in this case be?
addi tmp,val,-56
nor tmp,tmp,val
srwi tmp,tmp,31
now when comparing two variables that is different. But when one
of the operands is a constant there are lots of tricks to play
with using the complete set of Power/PPC logical instructions on
the sign bit.
>
> > The number of instructions do not correspond to the cost.
> >Compares, moving bits from condition registers, and bit extraction is
> >slower on newer PowerPC processors.
I'm quite surprised that integer compares have been affected, that's a
frequent operation and quite critical in a lot of applications. I was
not aware that rlwinm (and I suppose rlwimi/cntlzw/sraw/srawi and their
64 bit equivalents) are becoming slower (relative to add/subtract and
logical), but I suspect that this mostly affects high-end 64 bit
processors and not 32 bit variants for embedded systems.
Regards,
Gabriel