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Re: IA64 floating point division question
- From: Steve Ellcey <sje at cup dot hp dot com>
- To: zack at codesourcery dot com
- Cc: gcc at gcc dot gnu dot org
- Date: Tue, 31 Aug 2004 16:58:02 -0700 (PDT)
- Subject: Re: IA64 floating point division question
> I'm fairly sure that your problem is with the "*recip_approx"
> instruction, which is what is supposed to match this pattern. The
> catch is, it *only* allows XFmode operands, whereas you're trying to
> feed it SFmode.
No, I created some new versions of *recip_approx that "generate" SFmode
or DFmode (as well as some new _alts instructions) so that I can refer
to each register in only one mode. My new *recip_approx_sf instruction
is:
(define_insn "*recip_approx_sf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(div:SF (const_int 1)
(match_operand:SF 3 "fr_register_operand" "f")))
(set (match_operand:BI 1 "register_operand" "=c")
(unspec:BI [(match_operand:SF 2 "fr_register_operand" "f")
(match_dup 3)] UNSPEC_FR_RECIP_APPROX))
(use (match_operand:SI 4 "const_int_operand" ""))]
""
"frcpa.s%4 %0, %1 = %2, %3"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
> I'm not sure how to fix this. When I tried to do something similar, I
> got completely stuck because I couldn't make GCC refer to the *same*
> pseudo register in two different modes.
I believe that I am referring to every register in only one mode, I got
rid of all the
operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
statements that divsf3_internal_thr was using.
The problem is that I can match everything (including recip_approx_sf)
when I have "&& reload_completed" condition but I don't match the
recip_approx_sf instruction when I try to remove "&& reload_completed".
Steve Ellcey
sje@cup.hp.com