Re: RFC: Using mode and code macros in *.md files

[Steve Ellcey <sje at cup dot hp dot com>]

> That should certainly do the trick.  (Do you really want to
> include XF though?  I'm not sure whether it's OK to have
> (float_extend:XF (reg:XF ...)).)

You are right, I probably don't want to include XF, the unfortunate
aspect of this is that I probably need 6 versions of addxf then, one
version where one operand has a float_extend, one where both operands
are extended, and on where neither are extended.  I would also want each
of those to have a version where the result is truncated after the add
because on IA64 we can do that truncation as part of the single add
instruction.

One thought I had was this:  If there were an IF mode (infinite
precision), and a single basic floating point add for that mode

(set (match_operand:IF ...)
     (plus:IF (match_operand:IF ...)
              (match_operand:IF ...)))

and then there would be no basic add instruction for any other floating
point mode (SF, DF, or XF) then GCC will extend any of those to IFmode
to do the add.  I tested that and GCC did the float_extends.

Then all SF, DF, and XF addition could all be handled with one
macro'ized instruction:

;; AF == Any floating point type that can fit in a register.
(define_mode_macro AF0 [(SF "") (DF "") (XF "")])
(define_mode_macro AF1 [(SF "") (DF "") (XF "")])
(define_mode_macro AF2 [(SF "") (DF "") (XF "")])

(set (match_operand:AF0 0 "fr_register_operand" "=f")
     (float_truncate:AF0
       (plus:IF (float_extend:IF
                  (match_operand:AF1 1 "fr_register_operand" "%f"))
                (float_extend:IF
                  (match_operand:AF2 2 "fr_reg_or_fp01_operand" "fG")))))


Steve Ellcey
sje@cup.hp.com