Re: Problem with ColdFire restricted addressing modes (mode5.6combination)

[Peter Barada <peter at the-baradas dot com>]

>> So why did reload generate/accept this instruction which recog will
>> accept(since nonimmediate_operand/general_operand is valid for mode
>> 5/6), but the constraint combination doesn't?
>
>Reload is very complicated, and has lots of knobs.  I can't always just
>look at an instruction and figure out what happened.  Someone has to
>step through reload and see what happened.

I'll bet that I'm not the first persong to have looked through reload
and have my eyes glaze over trying to figure out what is does :)

>Perhaps the problem is that the 'Q' constraint is broken.  It just has a
>check for (MEM (REG)).  However, during reload, an unallocated
>pseudo-reg is equivalent to a stack slot, so this may not be doing what
>was intended.  You might need to add a check, and if reload_in_progress
>is true, then only accept a hard register here.

I tried rebuilding gcc-3.4.1 with the 'Q' EXTRA_CONSTRAINT being:

  (((C) == 'Q')					\
   ? (GET_CODE (OP) == MEM 			\
      && GET_CODE (XEXP (OP, 0)) == REG		\
      && (!reload_in_progress || ((REGNO (XEXP (OP, 0))) < FIRST_PSEUDO_REGISTER))) \

And the testcase still dies with:

./bug4.c:231: error: insn does not satisfy its constraints:
(insn 154 471 155 6 ./bug4.c:203 (set (mem/s:HI (plus:SI (reg:SI 9 %a1)
                (const_int 20 [0x14])) [4 <variable>.FAT_cnt+0 S2 A16])
        (mem:HI (plus:SI (reg/f:SI 14 %a6)
                (reg:SI 9 %a1)) [45 file_cnt+0 S4 A16])) 29 {*m68k.md:790} (nil)
    (nil))
./bug4.c:231: internal compiler error: in reload_cse_simplify_operands, at postreload.c:378

I noticed in gcc/config/rs6000/rs6000.h there's:

/* Optional extra constraints for this machine.

   'Q' means that is a memory operand that is just an offset from a reg.
   'R' is for AIX TOC entries.
   'S' is a constant that can be placed into a 64-bit mask operand
   'T' is a constant that can be placed into a 32-bit mask operand
   'U' is for V.4 small data references.
   'W' is a vector constant that can be easily generated (no mem refs).
   'Y' is a indexed or word-aligned displacement memory operand. 
   't' is for AND masks that can be performed by two rldic{l,r} insns.  */

#define EXTRA_CONSTRAINT(OP, C)						\
  ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG	\
   : (C) == 'R' ? legitimate_constant_pool_address_p (OP)		\

where 'Q' doesn't check for a hard register.  That seems
incorrect if I use your line of reasoning....

Any other suggestions?

-- 
Peter Barada
peter@the-baradas.com