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Re: cr logical instruction for powerpc target


On Tue, Aug 10, 2004 at 10:23:06AM -0400, David Edelsohn wrote:
> >>>>> =?ISO-8859-1?Q?R=E9gis Odey=E9?= writes:
> 
> Regis> I would like to understand when gcc generates CR logical instructions 
> Regis> (cror, crand,...) for powerpc target.
> 
> Regis> Any entry points for this quite specific question would be helpful.
> 
> 	GCC currently looks for opportunities to use CR logical
> instructions to compare the results of two comparisons.  GCC does not use
> CR logical instructions to cascade comparisons.

Last time I looked, it also used them for some floating point 
comparisons, like ">=" and "<=" which can't be taken as the 
negation of "<" and ">" because of NaNs. 

This is still the case if I read correctly rs6000.md:

; This pattern matches things like
; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68)(const_int 0))
;                                          (eq:SI (reg:CCFP 68)(const_int 0)))
;                                  (const_int 1)))
; which are generated by the branch logic.
[...]

On the other hand a few lines later, I don't understand why the length
attributes is larger than what I would naïvely expect:

;; Same as above, but get the GT bit.
(define_insn "move_from_CR_eq_bit"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))]
  "TARGET_E500"
  "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
  [(set_attr "type" "mfcr")
   (set_attr "length" "12")])
                       ^^

Why is it 12 when there are only 2 machine instructions
generated? 

Do I miss something (very likely, I've not followed
development very closely in the last 2 years) or is
the length attribute wrong for (almost) all the
patterns which include an mfcr/mfcrf instruction?

	Regards,
	Gabriel


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