This is the mail archive of the
mailing list for the GCC project.
Re: Why is x86_sahf_1 pattern disabled in x86_64?
On Fri, May 07, 2004 at 01:03:34PM -0700, H. J. Lu wrote:
> On Fri, May 07, 2004 at 09:28:14PM +0200, Jan Hubicka wrote:
> > > On Fri, May 07, 2004 at 01:11:54PM +0200, Uros Bizjak wrote:
> > > > According too ChangeLog, x86_sahf_1 pattern is disabled in x86_64 mode:
> > > >
> > > > Mon Mar 12 15:41:08 CET 2001 Jan Hubicka <email@example.com>
> > > > * i386.md (all XFmode patterns except swapxf): Disable for 64bit.
> > > > * i386.md (x86_sahf_1): Disable for 64bit.
> > > > (popsi*, pophi*): Likewise.
> > > > ...
> > > >
> > > > However, AMD64 software optimization guide shows sahf instruction as
> > > > DirectPath, latency 1 instruction. This instruction is needed in
> > > > modf()/drem() patterns to perform conditional jump on P flag set
> > > > [ix86_emit_fp_unordered_jump()) function in config/i386/i386.c].
> > >
> > > I think SAHF/LAHF were not present in the original amd64 specification;
> > > they got added back later on as a correction.
> > Assuming that sahf/lahf is in the amd64 specification now, it would be
> > OK to just revert the patch.
> I am trying to find out if it is supported on Intel EM64T. I will
> let you know what I get.
This is the current Intel's position:
Intel has no plans to support SAHF/LAHF on current processors or
future processors that include EM64T. Intel advises against using
those instructions. If those instructions are to be generated, they
should be under an architecture specific flag and not be included when the
compiler is expected to be generating portable code.
Because the opcodes (9e and 9f) are the IA32 opcodes, if Intel were to include
SAHF/LAHF in EM64T, Intel is likely to use those opcodes.