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Re: more m68k breakage on m68k-linux
Hi,
On Thu, 4 Mar 2004, Bernardo Innocenti wrote:
> > Can you please post the patch that corrects the FIXED_REGISTERS problem?
>
> I will. Please allow some time since I'm on a tight work schedule
> right now. I'll regtest the patch on m68k-linux and m68k-netbsd.
> Additionally, I'll build the m68k-uclinux kernel & userland.
Does your patch look very different from the one below?
That's the one I'm testing for m68k-linux right now.
bye, Roman
Index: config/m68k/m68k.c
===================================================================
RCS file: /cvsroot/gcc/gcc/gcc/config/m68k/m68k.c,v
retrieving revision 1.128
diff -u -r1.128 m68k.c
--- config/m68k/m68k.c 17 Feb 2004 20:24:44 -0000 1.128
+++ config/m68k/m68k.c 4 Mar 2004 11:25:54 -0000
@@ -44,6 +44,18 @@
#include "debug.h"
#include "flags.h"
+char regno_reg_class[] =
+{
+ DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
+ DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
+ ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
+ ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
+ FP_REGS, FP_REGS, FP_REGS, FP_REGS,
+ FP_REGS, FP_REGS, FP_REGS, FP_REGS,
+ ADDR_REGS
+};
+
+
/* The ASM_DOT macro allows easy string pasting to handle the differences
between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
support the %. option. */
Index: config/m68k/m68k.h
===================================================================
RCS file: /cvsroot/gcc/gcc/gcc/config/m68k/m68k.h,v
retrieving revision 1.109
diff -u -r1.109 m68k.h
--- config/m68k/m68k.h 15 Feb 2004 17:46:02 -0000 1.109
+++ config/m68k/m68k.h 4 Mar 2004 11:25:55 -0000
@@ -486,7 +486,10 @@
\
/* Floating point registers \
(if available). */ \
- 0, 0, 0, 0, 0, 0, 0, 0 }
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ \
+ /* Arg pointer. */ \
+ 1 }
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
@@ -497,7 +500,18 @@
#define CALL_USED_REGISTERS \
{1, 1, 0, 0, 0, 0, 0, 0, \
1, 1, 0, 0, 0, 0, 0, 1, \
- 1, 1, 0, 0, 0, 0, 0, 0 }
+ 1, 1, 0, 0, 0, 0, 0, 0, 1 }
+
+#define REG_ALLOC_ORDER \
+{ /* d0/d1/a0/a1 */ \
+ 0, 1, 8, 9, \
+ /* d2-d7 */ \
+ 2, 3, 4, 5, 6, 7, \
+ /* a2-a7/arg */ \
+ 10, 11, 12, 13, 14, 15, 24, \
+ /* fp0-fp7 */ \
+ 16, 17, 18, 19, 20, 21, 22, 23\
+}
/* Make sure everything's fine if we *don't* have a given processor.
@@ -636,12 +650,12 @@
{ \
{0x00000000}, /* NO_REGS */ \
{0x000000ff}, /* DATA_REGS */ \
- {0x0000ff00}, /* ADDR_REGS */ \
+ {0x0100ff00}, /* ADDR_REGS */ \
{0x00ff0000}, /* FP_REGS */ \
- {0x0000ffff}, /* GENERAL_REGS */ \
+ {0x0100ffff}, /* GENERAL_REGS */ \
{0x00ff00ff}, /* DATA_OR_FP_REGS */ \
- {0x00ffff00}, /* ADDR_OR_FP_REGS */ \
- {0x00ffffff}, /* ALL_REGS */ \
+ {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
+ {0x01ffffff}, /* ALL_REGS */ \
}
/* The same information, inverted:
@@ -649,7 +663,8 @@
reg number REGNO. This could be a conditional expression
or could index an array. */
-#define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
+extern char regno_reg_class[];
+#define REGNO_REG_CLASS(REGNO) ((enum reg_class)regno_reg_class[(REGNO)])
/* The class value for index registers, and the one for base regs. */