This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Fwd: Many questions

To: Solra Bizna <>

This address bounced.

On Sunday, October 26, 2003, at 05:15 PM, Solra Bizna wrote:
I have been assigned to find or create a C compiler, assembler, linker, etc. for the TCS architecture. Rather than writing my own compiler (something I do not look forward to trying) I would like to add TCS support to GCC (and binutils) if possible. However, I have several questions:

* Odd calling conventions
TCS function parameters and variables are stored in registers when possible. The TCS has 16 general-purpose registers, all are 64-bit integers. RE and RF are reserved for the frame pointer and stack pointer, respectively, and R0 is reserved for function return values. That leaves 13 registers for parameters and variables. Only the first 13 parameters are stored in registers, however, after that all are pushed onto the stack.
Varargs functions' parameters are loaded up to the last "static" argument, then pushed left-to-right.
Variables go after parameters in registers.
Now, these calling conventions cause problems. For example, what happens if the number of static arguments and variables exceeds 13? They should be swapped onto the stack, but GCC may have to be modified to compensate. Where would I perform the modifications allowing for these weird calling conventions?

This is not that odd, Sparc and rs6000 are similar. Take a look at those ports.

* Odd immediates
TCS instructions are 32 bits long. The low 16 bits (second in memory) store the instruction opcode, the high 16-bits store its operands. Each operand is 4-bit, allowing for instructions of the type
MA R2,R2,R4,R3 ; Multiply Add word
to be stored without trouble. Unfortunately, that limits immediates to either 4 or 12 bits (depending on the instruction). As a consequence, immediates must be embedded with code similiar to:

Most ports have limits to how big an immediate field can be in some instructions.
See, e.g., the I constraint on Sparc.

* Compiling 64-bit on 32-bit
Can GCC compile for 64-bit architectures on a 32-bit one? (specifically: powerpc-linux-gnu or powerpc-apple-darwin)


* Machine descriptions
I can no longer seem to find the machine description documentation. How do I write machine descriptions?

It's in the manual, which you find here:
Please read it, questions that are answered in the manual are not well received.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]