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64-bit on ia-32
- From: Johan Rydberg <jrydberg at night dot trouble dot net>
- To: gcc at gcc dot gnu dot org
- Date: Wed, 13 Aug 2003 00:30:43 +0200
- Subject: 64-bit on ia-32
Hi.
For a program I'm writing, I must use 64-bit datatypes on a IA-32
host. Since performance is everything for this application, I'm
looking at the code that GCC generates; and I have found something
that I think could be done better. Take the following example:
register unsigned long long v0 asm ("%esi");
union u
{
unsigned int ww[2];
unsigned long long ll;
};
extern int p1, p2;
#define P1 ((int) &p1)
#define P2 ((int) &p2)
static void
move1 (void)
{
v0 = (((unsigned long long) P1 << 32) & 0xffffffff00000000
| ((unsigned long long) P2) & 0xffffffff) ;
}
static void
move2 (void)
{
union u u1;
u1.ww[0] = P1;
u1.ww[1] = P2;
v0 = u1.ll;
}
This generates the following code with GCC 3.2.1 : (Flags is -O2
-fomit-frame-pointer)
move1:
movl $p1, %eax
pushl %ebx
xorl %ecx, %ecx
movl %eax, %ebx
xorl %edx, %edx
movl $p2, %eax
orl %edx, %ebx
orl %eax, %ecx
movl %ebx, %edi
movl %ecx, %esi
popl %ebx
ret
move2:
movl $p1, %eax
movl $p2, %edx
movl %eax, %esi
movl %edx, %edi
ret
What bothers me is the move2 function. Why don't move the value
to %esi:%edi directly? Even if the processor does a good job
executing these insns out-of-order, there is still the problem
with code size.
Is there a away that I can make GCC emit code that moves the
address of p1 and p2 to %esi and %edi, directly?
I've also tried this:
static void
move3 (void)
{
((union u) v0).ww[0] = P1;
((union u) v0).ww[1] = P2;
}
But GCC elminates the code (only a ret insn is emitted). Is
this done by the DCE optimization pass?
--
Johan Rydberg, Free Software Developer, Sweden
http://rtmk.sf.net | http://www.nongnu.org/guss/
Playing Punjabi MC Vs Dr Dre & Snoop D - Mundan To Episode (Promo)