RE: ideas for modeling pipeline with bypass registers?

["Nitin Gupta--SSW, Noida" <nitingup at noida dot hcltech dot com>]

> > How many such registers do you have in your target?
> 
> I don't see how it matters at the level of abstraction we are dealing
> with, but there are three functional-units: adder, barrel-shifter,
> logic, and each has a bypass register.
> 
> Greg
> 
Well this is what I understand about your target. Plz correct me if I am
wrong.
1. ALU has 3 units each with a bypass register.
2. These bypass registers are exclusivey for these functional units only.
3. Each ALU operation will use the bypass register depending on the
function.
4. The bypass register can be explicitly used for reading but not writing
any value to it.


Then probably it might  nit be possible to abstract two byepass registers.
since according to the timing analysis given by you:

        insn-0: bypass-even <- r2 + r3;
        insn-1: bypass-odd <- bypass-even + r5;
        insn-2: [ r1 <- bypass-even; bypass-even <- r2 + bypass-odd; ]
        insn-3: r4 <- bypass-odd 
        insn-4: r6 <- bypass-even

insn-0 will use the adder-bypass register and similarly insn-1 also.thus in
insn-2 you will have the clobbered value of bypass register. Hence under the
above assumptions your strategy won't be possible to implement.

Just one thought that if you have the timing analysis of pipeline then
probably you can have following type of timin analysis using just one bypass
register:

        insn-0: bypass <- r2 + r3;
        insn-1: [ r1 <- bypass; bypass <- bypass + r5; ]	<-- here
        insn-2: [r4 <- bypass;  bypass <- r2 + bypass; ]	<-- here
        insn-3: r6 <- bypass

The instructions marked "here" will actually be possible if the pipeline
allows such a register read/write mechanism. This can be clear from the
timing analysis of the pipeline.

~Nitin