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Re: ideas for modeling pipeline with bypass registers?
- From: Greg McGary <greg at mcgary dot org>
- To: <tm_gccmail at mail dot kloo dot net>
- Cc: gcc at gcc dot gnu dot org, greg at mcgary dot org
- Date: 28 Jul 2003 17:11:05 -0700
- Subject: Re: ideas for modeling pipeline with bypass registers?
- References: <Pine.LNX.4.21.0307281618320.15582-100000@mail.kloo.net>
<tm_gccmail@mail.kloo.net> writes:
> On 28 Jul 2003, Greg McGary wrote:
>
> > I'm working on a GCC port to a pipelined machine that has 1 insn
> > latency between ALU operation and numbered-register writeback
> > (i.e., insn-0: ALU op
> > insn-1: ...
> > insn-2: ALU op result appears in destination register
> >
> > In order to make ALU ops available with no latency, there's a special
> > "bypass" register that can be used before the register-file writeback.
> > This bypass value is available for only one cycle, after which it is
> > clobbered by the next ALU op.
>
> I'm assuming this bypass register is an architecturally visible register?
Yes, it is visible. It can be named as a source operand in most every
context that the ordinary register-file members can.
Greg