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Re: Pre_dec and Post_inc insns
- From: Hans-Peter Nilsson <hp at bitrange dot com>
- To: tm_gccmail at mail dot kloo dot net
- Cc: Natasha Wilson <nat_w at operamail dot com>, <gcc at gcc dot gnu dot org>
- Date: Wed, 9 Jul 2003 23:08:22 -0400 (EDT)
- Subject: Re: Pre_dec and Post_inc insns
On Wed, 9 Jul 2003 tm_gccmail@mail.kloo.net wrote:
> The instruction scheduler should have maximum freedom to reorder
> instructions, which means pre/post increment/decrement addressing modes
> should be generated after sched1.
Let's keep it open for each port to decide, ok? I can't see how
it will hurt you. :-)
> For your processor with a load latency of one clock, the instruction
> scheduler should not reorder the load instructions so the natural
> postincrements should be generated. If this is not happening, then this is
> a problem with the machine description or the scheduler.
I haven't given you all details on "my processor", so it seems
you jump to conclusions, for example regarding the cost of an
address load insn and its latency vs. postincrement on this
target. No, I don't *know* which approach will win, but I don't
want a particular one forced on me, thank you.
> If this problem is "solved" by generating pre/post dec/inc before sched1,
> then you are merely fixing the symptom and not the root problem. So, I
> stand by my assertion that pre/post inc/dec should be generated after
> sched1.
Just please don't try and force that view.
brgds, H-P