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Re: Optimizing for Low Power Consumption
- From: Peter Barada <pbarada at mail dot wm dot sps dot mot dot com>
- To: cwolff at cs dot uml dot edu
- Cc: gcc at gcc dot gnu dot org
- Date: Tue, 3 Jun 2003 15:58:56 -0400
- Subject: Re: Optimizing for Low Power Consumption
- References: <Pine.LNX.4.44.0306031530280.2497-100000@mercury.cs.uml.edu>
>I'm working on a research project concerned with reducing the power
>consumption of programs running on embedded systems. The m68hc11 is one
>of the chips we are working with. I would like to modify gcc's backend
>for this target to select the instructions with the lowest cost in terms
>of power consumption. It seems that this could be implemented using
>peephole optimization.
>
>As someone who is unfamiliar with the internals of gcc, can anyone tell me
>what the scope of this project would be, and if it is a realistic goal for
>a short-term summer project?
Before anyone can even try to scope this, it would help immeasurably
to provide some examples of what's a high-power instruction sequence, and
then its equivalent low-power instruction sequence. Then we might be
able to suggest an approach you could use. The more sequences you
provide, the better we can make suggestions.
As for dealing with the internals of gcc, Read the manual; it will
make your life much easier....
See http://gcc.gnu.org/onlinedocs/gccint/index.html for the online
version.
Personally I prefer to print the whole manual from a gcc distribution
and then scribble notes in the margins...
--
Peter Barada Peter.Barada@motorola.com
Wizard 781-852-2768 (direct)
WaveMark Solutions(A Motorola Company) 781-270-0193 (fax)