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Unaligned half-word load (ARM)
- From: Shaun Jackman <sjackman at pathwayconnect dot com>
- To: gcc at sources dot redhat dot com
- Date: 29 May 2003 11:51:53 -0600
- Subject: Unaligned half-word load (ARM)
- Organization: Pathway Connectivity
GCC is generating an odd instruction sequence that's causing me a bus
fault. perhaps somebody here can expalain it to me.
uint16_t* p = (a 32 bit aligned address);
uint16_t foo = *p;
GCC generates
ldr r1, [r5, #2] @ load-rotate
mov r1, r1, lsr #16
where r5 has the 32 bit aligned address. This causes a bus-fault since
r5+2 is on a 16 bit boundary (but not 32), and attempts a 32-bit load
from a 16-bit boundary. What's gone wrong?
arm-wince-pe-gcc (GCC) 3.2
My target is an ARMSA1110 (Compaq iPAQ Pocket PC).
Please cc me in your reply.
Thanks,
Shaun