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Re: An issue for the SC: horrible documentation quality of GCC


    Which, in RTL is

      (set b (plus (mult d 4) b))
      (set c (plus (mult d 4) c))

    into 

      (set t1 (mult d 4))
      (set b (plus t1 b))
      (set c (plus t1 c))

    is a de-optimization (takes 3 cycles instead of 2).

It's long been on my list to try to see if can find some way to turn the
latter back into the former.  The problem is that combine won't do it 
because it doesn't know it can kill T1.  But I've never come up with
any way that does it.  I think this sort of thing is very common,
especially with addressing modes on CISC machines.


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