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Re: Address Arithmetic Improvement
- From: <tm_gccmail at mail dot kloo dot net>
- To: "Rakesh Kumar - Software, Noida" <rakeshku at noida dot hcltech dot com>
- Cc: gcc at gcc dot gnu dot org, Alexandre Oliva <aoliva at redhat dot com>,Jan Hubicka <jh at suse dot cz>
- Date: Wed, 9 Apr 2003 13:09:45 -0700 (PDT)
- Subject: Re: Address Arithmetic Improvement
On Wed, 9 Apr 2003, Rakesh Kumar - Software, Noida wrote:
> Processor: SH4
> Mode: Little Endian
>
> On compiling the attached program with -O2, I observed that reload pass
> splits up the DF mode address arithmetic insn into SF mode insns using FPSCR
> register.
>
> I believe SH4 has the restriction that in little endian, we can't use
> double-precision floating-point moves between memory and registers.
>
> But generating two insns, where one would suffice, encourage redundancy.
> Also to adjust the pointers, we are generating additional insns as defined
> in define_split in sh.md.
>
> I propose that one function could be developed which scans the basic block
> and combines address arithmetic insns. But I'm not clear about where to put
> it so that it should not affect the present compilation process.
>
> Can anybody there suggest me some alternative?
>
> Thanks in advance
> Rakesh Kumar
>
I think regmove is supposed to do this, but it runs too early to catch the
post-reload DFmode splits.
I was thinking about this problem a few weeks ago, and it may be possible
to use the peep2 pass to opportunistically combine multiple adds into a
single add instruction, such as:
fmov.s @r0+,fr0
fmov.s @r0,fr1
add #-4,r0
...
add #64,r0
fmov.s @r0+,fr2
fmov.s @r0,fr3
into
fmov.s @r0+,fr0
fmov.s @r0,fr1
...
add #60,r0
fmov.s @r0+,fr2
fmov.s @r0,fr3
Toshi