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RE: An unusual Performance approach using Synthetic registers
- From: Chris Lattner <sabre at nondot dot org>
- To: Andy Walker <ja_walker at earthlink dot net>
- Cc: gcc at gcc dot gnu dot org
- Date: Fri, 27 Dec 2002 03:03:48 -0600 (CST)
- Subject: RE: An unusual Performance approach using Synthetic registers
> I am modifying gcc to add Synthetic registers. If I am mistaken, this
> is a big waste of time. If I am correct, (meaning "really really
> Lucky") then this may provide a significant increase in speed for
> executables.
IMHO, this could be a much bigger win on modern processors than you might
think. You may win a suprising amount strictly because of the register
renaming hardware found on modern x86 processors, which would eliminate
the L1 reference. Take a look at this paper, for example, which describes
a very similar approach:
http://cm.bell-labs.com/cm/cs/what/smlnj/compiler-notes/k32.ps
On the other hand, I think this approach is not the right one to take if
improving optimizer effectiveness is the goal. IMHO, more stuff should
be done on a mid-level representation, such as treessa, than the
low-level RTL... but the infrastructure appears to not be ready yet.
You will probably find that the number of "virtual" registers varies
widely across different incarnations of the architecture, implying that
the -march options should change the number of virtual registers. Maybe
keeping this in mind when you design the code will help down the line. :)
This will certainly be an interesting project, please keep the list
informed with what you find. :)
-Chris
--
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