The correct way to clobber a condition register for DFA scheduling

[Dan Towner <dant at picochip dot com>]

Hi all,

I am writing a gcc port for a 16-bit DSP. Until now, I have ignored 
condition codes by using the cbranch pattern, and generating the flag, 
and branch in one output template. I have now split the branch into 
separate compare and branch instructions, which allows the two to be 
scheduled properly using the DFA scheduler. This also means that I have 
to ensure that other instruction patterns which affect the condition 
flags must now rewritten to correctly to show that they cannot be 
inserted between related compare and branch instructions. For example, I 
use the following pattern for an addhi3 instruction:

(define_insn "addhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
	(plus:HI (match_operand:HI 1 "register_operand" "r,r,r")
		 (match_operand:HI 2 "general_operand" "r,M,n")))
   (clobber (reg:CC CC_REGNUM))]
  ""
  "* return picochip_addhi3(operands);")

Note that the instruction clobbers the CC register. Unfortunately, when 
I run some tests, I get internal errors for a lot of my tests - the 
number of deaths of registers differs (as determine by 
sched-rgn.c:schedule_insns), but only in instructions which appear to be 
unrelated in the addhi pattern. I can cure these errors by removing the 
mode of the condition register, so that it becomes:

(clobber (reg CC_REGNUM))

I no longer get internal errors with this pattern, but then the DFA 
scheduler incorrectly schedules addhi3 instructions between related 
compare and branch instructions. This is only cured by using the :CC 
mode specifier, which leads back to the first problem.

Is the above pattern the correct way to clobber the CC register, or is 
there a better way?

Thanks,

Dan.

=============================================================================
Daniel Towner
picoChip Designs Ltd., Riverside Buildings, 108, Walcot Street, BATH, 
BA1 5BG
dant@picochip.com
07786 702589