Re: Status of SSE builtins

[Jan Hubicka <jh at suse dot cz>]

> >  4) Missaligned load/store buitins
> >     The use of missaligned loads/stores results in GCC eventually
> >     keeping the values in register and producing "internal" move for it
> >     resulting in trap.  I am not sure how to model this properly.
> 
> Make the misaligned load explicit as a special operation.
> You can use insv / extv in your pattern, or use two memory references
> that are explicitly aligned upwards / downwards and put the pieces
> together with arithmetic.
I guess I need to use 16 byte memory references to be strictly correct,
or perhaps jus tuse BLKmode memory reference would work.
> 
> > 5) generic SIMD support is quite broken right now as SSE does not
> >     allow scalar opration on elements of vectors registers, like Sparc and
> >     other sane instruction sets most probably do.  I am not quite sure how
> >     to get arround here and I also think the RTL produced is invalid when
> >     dealing with vectors containing elements smaller than word size. 
> 
> Can you give an example?

You can compile any of the simd-*.c testcases from testsuite.
I've sent few emals about previously.
We generate instruction dealing with elements of the vector using
subregs, like (subreg:HI (reg:V4HI) 2) is expected to access and modify
only the second field of the vector.  However the subregs gneerally
clobber whole word in GCC and are not allowed in such general forms.

The SIMD support works for PPC/SPARC as such subregs always simplify to
specific register, but for SSE they not.

Honza
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